RTL Design Engineer, Hardware

Job Title

RTL Design Engineer, Hardware

Role Summary

Design and implement high-performance RTL for AI accelerator subsystems and related SoC components. Own substantial portions of the design from micro-architecture through implementation, and drive functionality, performance, power, and area (PPA) targets.

Work closely with compiler, performance modeling, verification, and physical design teams to resolve bottlenecks and bring silicon to reliable tapeout and post-silicon operation.

Experience Level

Mid-level - expects approximately 5+ years of industry experience working on advanced process nodes.

Responsibilities

Deliver RTL and architecture for high-performance AI/SoC blocks and integrate with backend and software teams.

• Create high-level architectural specifications and detailed micro-architectures for AI hardware subsystems.
• Design and implement complex logic in SystemVerilog focused on pipelines, throughput/latency trade-offs, and power-efficient data paths.
• Collaborate with backend/physical design on synthesis, floorplanning, power analysis, and static timing analysis (STA); resolve timing violations to meet target frequencies.
• Identify and resolve performance bottlenecks with compiler, performance modeling, and software teams across ISA, micro-architecture, and system-level layers.
• Take ownership of large blocks of the design, drive ECOs, and ensure functional, performative silicon delivery.
• Work with verification and post-silicon teams to debug issues and close the loop from RTL to silicon.

Requirements

Must-have technical skills and experience for successful candidates.

• 5+ years practical industry experience working with advanced process nodes (7nm or below).
• Deep hands-on proficiency with RTL and synthesis/physical/timing toolflows (SystemVerilog; simulation, debug and synthesis/timing tools such as VCS/Verdi, Fusion Compiler, PrimeTime or equivalents).
• Expert knowledge in computer architecture for at least one chip class (SoC, CPU, GPU, or AI accelerator).
• Proven track record of delivering functional and performant silicon, including handling ECOs and reliable silicon at scale.
• Strong collaboration skills to co-design across teams (compiler, software, verification, physical design).
• Preferred (nice-to-have): post-silicon bug fixing and low-level debugging (GPIO/I2C/SPI/UART), firmware patching, proficiency in C/C++/Python and ISA assembly, and experience with high-speed IO (PCIe, UCIe) or memory controllers (HBM/DDR) and NoC protocols (AXI, CHI, credit/valid-ready).

Education Requirements

Bachelor's degree in Electrical Engineering or Computer Engineering is specified. The role also requires 5+ years of practical industry experience working on advanced process nodes (7nm or below).

About the Company

Company: River AI

Headquarters: Austin, TX, USA

River AI builds personal AI systems by developing custom hardware, training infrastructure, and user interfaces to enable local, user-owned AI. The team comprises engineers and researchers from leading tech companies and AI labs focused on AI accelerators, SoC design, and end-to-end stack co-design.