RTL Design Engineer

Job Title

RTL Design Engineer

Role Summary

Design and implement RTL for advanced PLL IPs within an ASIC/analog-mixed-signal engineering team. The role covers microarchitecture, RTL modeling, and driving designs through implementation to silicon while collaborating with verification and physical design teams.

Experience Level

Mid-level — typically 5+ years of RTL design experience.

Responsibilities

Primary duties include:

• Analyze complex digital design problems and propose architectural solutions.
• Develop Verilog RTL and functional behavioral models for current and future IPs.
• Create microarchitecture specifications and drive ASIC design flows with supporting scripts.
• Collaborate with Design Verification and Physical Design teams to ensure functional correctness and timing closure.
• Deliver design improvements, optimizations, and power-saving enhancements; support silicon bring-up and diagnostics.

Requirements

Must-have skills and experience:

• 5+ years of progressive RTL design experience.
• Strong proficiency in Verilog and RTL design methodologies.
• Proven ability to analyze complex digital designs and drive tasks independently to completion.
• Ability to mentor junior engineers and communicate effectively within a team.
• Experience collaborating with verification and physical design teams and working within ASIC design flows.

Nice-to-have:

• Proven experience in analog mixed-signal design from specification to silicon, including PLL-related work.
• Experience with high-speed interfaces (DDR, GDDR, HBM, SERDES) and multi power/clock-domain designs.
• Familiarity with industry-standard ASIC CAD tools for simulation, synthesis, STA, CDC, UPF, and power estimation.

Education Requirements

Master's degree preferred; relevant academic background expected.

About the Company

Company: Tanisha Systems

Engineering services company focused on wireless communications, FPGA development, and embedded systems, supporting 5G/6G and broadband technology projects.