RTL Design Engineer (ASIC) – AI Accelerators

Job Title

RTL Design Engineer (ASIC) – AI Accelerators

Role Summary

Design, implement, and test RTL components for a vision AI accelerator, and support PCIe IP integration into SoCs. Work remotely with system architects, verification, physical design, and software teams to meet performance, power, and area (PPA) targets.

This role focuses on front-end RTL development, integration activities, and collaboration across verification and physical design to deliver production-quality silicon building blocks.

Experience Level

Mid-level — typically requires about 5+ years of RTL design experience, with industry experience expected.

Responsibilities

Primary responsibilities include RTL development, integration, verification support, and PPA-driven trade-offs.

• Manage and develop synthesizable Verilog/SystemVerilog RTL for complex AI accelerator subsystems.
• Define micro-architectures from high-level product specifications.
• Integrate complex IPs (e.g., PCIe) into SoCs and perform front-end integration tasks (lint, CDC checks, synthesis, ECO).
• Develop SystemVerilog assertions, constraints, checkers, and testbenches in coordination with verification teams.
• Debug RTL using simulation tools and waveform viewers to ensure functional correctness and coverage closure.
• Collaborate with physical design teams on timing closure, synthesis, static timing, DFT, and ECO flows.
• Perform PPA trade-offs and drive architectural decisions to meet project goals.
• Coordinate with system architects to align specifications and requirements.

Requirements

Must-have technical skills and practical experience required to perform the role.

• 5+ years of RTL design experience with practical industry experience in digital design.
• Strong digital design fundamentals, including finite state machines and clock domain crossing techniques.
• Proficiency in SystemVerilog and writing synthesizable, reusable RTL.
• Experience with front-end EDA tools (simulators, linters, CDC checkers) and familiarity with synthesis and static timing analysis.
• Knowledge of DFT and ECO flows and front-end integration activities.
• Scripting proficiency (Perl, Python) for automation and productivity improvements.
• Ability to debug using simulation tools and waveform viewers and to optimize RTL for PPA.
• Basic familiarity with memory compilers and deep learning/ML concepts relevant to accelerator design.

Nice-to-have:

• Prior RTL work on microprocessors, SoCs, memory micro-architecture, or interconnect IP.
• Experience with SoC interconnect protocols (AXI4, AXI-Stream, AHB) and compute subsystem memory designs.
• Experience integrating and simulating PCIe interfaces and working with verification IP and SystemVerilog assertions.
• Experience designing hardware to accelerate deep neural networks.

Education Requirements

Master's or PhD in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Mentium Technologies

Developer of vision AI accelerators and hardware–software libraries. Designs digital AI accelerator SoCs and RTL components, integrating IP such as PCIe and collaborating across architecture, verification, physical design, and software teams to deliver high-performance machine and deep learning solutions.