RTL Design Engineer

Job Title

RTL Design Engineer

Role Summary

Write production-grade Verilog/SystemVerilog for Snowcap's superconducting digital chips and own RTL blocks end-to-end from microarchitecture spec to implementation. Work directly with microarchitecture, design verification, and implementation teams in a small, cross-functional organization to deliver synthesizable, testable RTL that meets timing, area, and power objectives.

Experience Level

Mid-level. The posting does not specify years of experience.

Responsibilities

Deliver and maintain RTL and related artifacts; collaborate across teams to drive blocks to clean implementation.

• Implement synthesizable Verilog/SystemVerilog from microarchitecture specifications and own the block from code to clean implementation.
• Write block-level unit tests and assist with verification testbench development around your blocks.
• Run and address lint, CDC, and static-check findings; deliver clean RTL rather than temporary waivers.
• Drive synthesis runs, read timing reports, and revise RTL for QoR tradeoffs (area, timing, power).
• Participate in code reviews and architecture walkthroughs; establish and follow RTL coding standards and conventions.
• Work with the implementation team to resolve synthesis and timing issues specific to the non-CMOS logic family.
• Provide implementable alternatives when microarchitecture specifications are not realizable.

Requirements

Must-have skills and behaviors.

• Strong Verilog and SystemVerilog coding skills with production-quality RTL experience on taped-out chips.
• Deep, working understanding of synthesizable constructs and their effects on area, timing, and power.
• Experience with logic synthesis tools (Synopsys DC, Cadence Genus, or equivalent) and the discipline to interpret timing and QoR data.
• Design-for-testability practices: structural assertions, parameterization, and testable RTL.
• Working knowledge of lint, CDC, and static checking flows and the discipline to deliver clean RTL.
• Comfort operating in an early-stage environment with evolving specs and flows.

Nice-to-have:

• Ability to span microarchitecture and RTL and to push back on specs with implementable proposals.
• Track record with complex RTL/IP (memory subsystems, MAC/PCS, high-speed interconnects).
• Experience with custom or non-standard logic families (asynchronous, wave-pipelined, SFQ, PCL, AQFP, RSFQ).
• Background at leading silicon teams with shipped silicon and experience authoring RTL standards or reusable IP.
• Familiarity with formal verification, equivalence checking, and assertion-driven design.

Education Requirements

Not specified.

About the Company

Company: Snowcap Compute

Headquarters: San Francisco, CA, United States

Snowcap Compute develops commercial superconducting digital computers using Josephson junction–based PCL logic that operate at cryogenic temperatures, aiming for dramatically lower power than CMOS. The company combines expertise in quantum physics, cryogenic engineering, and semiconductor manufacturing to build production superconducting chips.