RTL Design Engineer

Job Title

RTL Design Engineer

Role Summary

Design and implement RTL for digital semiconductor blocks, focusing on coding, debugging, synthesis, timing closure, and design-for-test. The role works with architecture, verification, and physical design teams to deliver silicon-ready RTL.

Experience Level

Senior — the posting requests a candidate with 7+ years of relevant RTL/VLSI experience.

Responsibilities

The core responsibilities include:

• Design, code, and maintain RTL for digital blocks using Verilog.
• Perform synthesis, static timing analysis (STA), and fix timing violations.
• Analyze and resolve CDC (clock domain crossing) issues.
• Implement and validate DFT structures and support test insertion flows.
• Collaborate with verification and physical design teams to debug integration issues.
• Optimize designs for power, area, and performance.
• Develop automation and scripts to support flows (Python, TCL).
• Integrate and validate standard interfaces such as AMBA and PCIe.

Requirements

Must-have technical skills and experience, plus a few desirable additions.

• Must-have: 7+ years of RTL design experience in VLSI.
• Must-have: Strong experience with Verilog and RTL coding best practices.
• Must-have: Practical experience with synthesis and static timing analysis (STA).
• Must-have: Experience with CDC analysis and resolution.
• Must-have: Design-for-test (DFT) experience and test structure implementation.
• Must-have: Scripting/automation skills (Python, TCL) to support design flows.
• Must-have: Experience with low-power design techniques.
• Nice-to-have: Experience integrating AMBA and PCIe interfaces.

Education Requirements

Not specified.

About the Company

Company: IBA Infotech

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