RTL Design Engineer
Design and implement CPU microarchitecture and RTL for high-performance RISC-V cores. Work within a cross-functional engineering team covering microarchitecture, verification, performance modeling, and physical implementation to deliver silicon IP that meets frequency, area, and power targets.
Position based in Hsinchu, Taiwan; candidates must have the legal right to work in Taiwan and may be subject to export-control authorization checks.
Mid-level. No specific years stated; requires prior CPU RTL design experience.
Primary responsibilities include:
Must-have and preferred skills:
Must-have:
Nice-to-have:
BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent practical experience.
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
