RTL Design Engineer

Job Title

RTL Design Engineer

Role Summary

Design and integrate digital control logic for high-speed mixed-signal PHY/IP, focusing on RTL micro-architecture, implementation closure, and interfacing with analog subsystems. Work within a cross-functional engineering team that includes analog designers, verification engineers, and architecture leads to deliver production silicon IP.

Experience Level

Senior level: minimum 5+ years of ASIC/IP RTL design experience (experience expectation stated in source).

Responsibilities

Primary responsibilities include RTL design, digital-analog interface work, verification support, and silicon bring-up.

• Own micro-architecture and RTL implementation (SystemVerilog/Verilog) for digital control blocks in PHY (e.g., PCS, calibration engines, power states, clock/reset distribution).
• Define and verify the digital/analog interface boundary; implement calibration algorithms for analog blocks (RX equalization, TX driver settings, PLL/DLL tracking).
• Ensure protocol compliance and correct integration with Data Link layer interfaces (such as PIPE).
• Drive front-end design-closure activities: linting, CDC analysis, formal verification (LEC), static timing constraints and STA preparation.
• Collaborate with AMS simulation and DV teams to debug co-simulation failures and improve functional coverage.
• Support post-silicon validation, bring-up, and debug to diagnose silicon issues and optimize calibration/firmware parameters.

Requirements

Must-have technical skills and hands-on experience; a few preferred skills listed separately.

• Must-have: 5+ years of ASIC/IP RTL design experience with strong SystemVerilog/Verilog skills.
• Must-have: Practical experience with high-speed SerDes architectures and PIPE interface standards.
• Must-have: Experience with front-end design tooling and flows: linting/CDC (e.g., SpyGlass), formal verification (e.g., JasperGold or equivalent), and STA-ready constraint generation.
• Must-have: Knowledge of multi-clock designs, clocking/reset domains, low-power techniques (UPF, clock gating), synthesis fundamentals, and CDC handling.
• Must-have: Familiarity with digital/analog boundary issues, asynchronous signal handling, handshakes, and mixed power-domain interaction.
• Must-have: Experience supporting post-silicon bring-up, validation, and cross-team debug activities.
• Nice-to-have: Hands-on experience with analog calibration algorithms (RX equalization, TX impedance tuning), PLL/DLL behavior, PHY/PCS design, and automation scripting for flows.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics and Communication, or a related discipline.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.