RTL Design Engineer

Job Title

RTL Design Engineer

Role Summary

Own top-level RTL design and integration for mixed-signal power-management IP on SoCs, driving designs through timing closure and tape-out.

Collaborate with analog, firmware, verification, and physical-design teams to deliver production silicon and support post-silicon bring-up.

Experience Level

Mid-level. Role expects engineers with experience owning RTL blocks or subsystems through timing closure and tape-out and mentoring junior engineers.

Responsibilities

Primary technical and integration responsibilities for top-level RTL and chip delivery:

• Own top-level RTL design and integrate analog macros for mixed-signal power-management ICs.
• Partner with analog teams to integrate and debug analog behavioral models in the digital simulation environment.
• Author micro-architecture specifications with Architecture and Firmware teams.
• Serve as primary interface to Physical Design for timing closure; create and review SDC constraints and clock-domain crossings.
• Drive timing closure, ECO support, and manage area/power/floorplan trade-offs through tape-out.
• Perform RTL signoff before PD releases: lint, CDC/RDC, synthesis quality, and connectivity checks.
• Define and review verification test plans and coverage goals with verification teams; debug block- and system-level simulation failures.
• Support post-silicon bring-up and silicon-to-RTL correlation.
• Mentor junior engineers and lead design reviews; collaborate across Analog, Firmware, Systems Engineering, and Architecture teams.

Requirements

Key technical requirements and preferred skills.

• Strong RTL design expertise in SystemVerilog with ownership of blocks or subsystems through tape-out (must-have).
• Hands-on experience developing SDC timing constraints and driving timing closure on production silicon (must-have).
• Proficiency with synthesis, lint, and CDC/RDC tools and flows (must-have).
• Strong scripting skills (Python and TCL) for flow automation and debug (must-have).
• Top-level SOC or chip-level integration experience on mixed-signal devices (must-have).
• Experience integrating and debugging analog behavioral models in digital simulations (Verilog-AMS, real-number/wreal) (must-have).
• Low-power design methodology and UPF-based power intent experience (preferred).
• Familiarity with power-management control interfaces (I2C, SPI, APB, SVID/PMBus) (preferred).
• Post-silicon bring-up and silicon-to-RTL correlation experience (preferred).
• Strong communication and cross-functional collaboration skills; ability to lead design reviews (must-have).
• This role is not eligible for visa sponsorship.

Education Requirements

Bachelor's or master's degree in Electrical or Computer Engineering.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.