RTL Design Engineer

Job Title

RTL Design Engineer

Role Summary

Design and integrate digital RTL for high-speed mixed-signal IP, focusing on digital control blocks that interface with SerDes PHYs. Work with analog designers, verification engineers, and architects to deliver silicon-ready IP with attention to power, timing, and protocol compliance.

Experience Level

Entry-level (0–3 years). The posting specifies a minimum of 2+ years of ASIC/IP RTL design experience.

Responsibilities

Key responsibilities for this role include:

• Own micro-architecture and RTL development (SystemVerilog/Verilog) for PHY control blocks such as PCS, calibration engines, power-management states, and clock/reset distribution.
• Define and verify digital-analog interface boundaries and implement calibration algorithms for analog components (RX equalization, TX driver impedance, PLL/DLL tracking loops).
• Ensure protocol and IP compliance (e.g., PIPE interfaces) and integrate with higher-level data link requirements.
• Drive front-end design closure activities: linting, CDC analysis, formal verification (LEC), and static timing constraints generation for synthesis/STA.
• Collaborate with AMS simulation and Design Verification teams to debug co-simulation issues and maximize coverage.
• Support post-silicon validation, bring-up, and debug to root-cause silicon issues and tune calibration/firmware parameters.

Requirements

Must-have technical skills and experience:

• Minimum 2+ years of ASIC/IP RTL design experience focused on digital logic for PHY/SerDes domains.
• Proficiency in SystemVerilog/Verilog and RTL coding best practices.
• Strong working knowledge of high-speed SerDes architectures and PIPE interface standards.
• Experience with front-end verification and design tools such as lint/CDC tools, formal verification tools, and STA flows.
• Understanding of multi-clock designs, low-power techniques (e.g., UPF, clock gating), and synthesis/STA fundamentals.
• Experience managing digital/analog boundaries, asynchronous signals, handshakes, and multiple power domains.
• Experience supporting silicon bring-up and post-silicon debug.

Nice-to-have:

• Experience implementing calibration algorithms for analog components and working directly with AMS simulation teams.
• Familiarity with specific EDA tools named in large ASIC/SoC flows (examples: Synopsys SpyGlass, Cadence JasperGold) or equivalent tools.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics & Communication, or a related discipline.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.