RTL Design Engineer 5

Job Title

RTL Design Engineer 5

Role Summary

Design and verify RTL for ASIC/SoC projects, implement features in Verilog HDL, and debug RTL and integration issues. The role interfaces with architecture, synthesis, and backend teams to deliver silicon-ready RTL.

Benefits mentioned: health insurance and 401(k).

Experience Level

Senior-level — requires 10+ years of relevant RTL/ASIC design experience.

Responsibilities

Primary duties include implementing RTL from architecture, verifying functionality, and supporting physical implementation.

• Implement and debug RTL using Verilog HDL for new and modified functions.
• Read and interpret SoC-level architectural specifications and translate to microarchitecture.
• Write microarchitecture specifications for assigned features.
• Perform linting and simulation of designs to ensure quality and functional correctness.
• Collaborate with synthesis and backend teams for timing closure and physical implementation.

Requirements

Must-have technical skills and experience.

• 10+ years of professional RTL/ASIC design experience.
• Proven experience with Verilog HDL for RTL implementation and debug.
• Experience performing linting and running digital simulations for verification.
• Experience collaborating with synthesis and backend teams on physical implementation.
• Ability to produce clear microarchitecture/specification documents from SoC-level requirements.

Education Requirements

Bachelor's or Master's degree in Computer Engineering (as stated in the posting).

About the Company

Company: Mindlance

A staffing and workforce solutions firm that provides recruitment, contract staffing, and consulting services across IT, engineering, and professional domains to connect employers with skilled talent.