RTL Design Engineer
VoltaiJob Title
RTL Design Engineer
Role Summary
Design and own RTL for production silicon from microarchitecture through signoff-ready SystemVerilog. Work across front-end and back-end teams, verification and formal groups, and with customer design teams on real chip programs. Also review and evaluate AI-generated RTL to help define high-quality design standards.
Experience Level
Mid-level; typically requires 5+ years of RTL design experience on chips that taped out.
Responsibilities
Key responsibilities include:
- Own microarchitecture and implement RTL for IP blocks and subsystems in SystemVerilog.
- Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.
- Partner with verification and formal teams on test plans, assertions, and coverage closure.
- Debug complex functional and timing issues across simulation, emulation, and silicon.
- Review and evaluate AI-generated RTL and help define correctness and quality standards.
- Collaborate directly with customer design teams when required.
Requirements
Must-have skills and experience:
- 5+ years of RTL design experience on chips that taped out.
- Expert SystemVerilog/Verilog knowledge and strong microarchitecture skills.
- Hands-on experience with lint, CDC, synthesis flows, and timing-aware design.
- Familiarity with common protocols (AXI, PCIe, Ethernet, DDR, or similar).
- Practical scripting experience in Python or Tcl.
Nice-to-have:
- Experience writing SVA or working with formal verification.
- Low-power design experience (UPF, clock and power gating).
- Interest or experience with AI-assisted design tools.
Education Requirements
Not specified.
About the Company
Company: Voltai
Headquarters: Palo Alto, CA, United States
Voltai develops AI-driven world models and agents to design, evaluate, and optimize physical systems-focusing on hardware, electronics, and semiconductors to enable AI-led hardware co-design, performance modeling, and cross-domain optimization.
