RTL Design Director (SoC Lead)

Job Title

RTL Design Director (SoC Lead)

Role Summary

Director-level SoC lead responsible for architecture, micro-architecture, and RTL direction for next-generation switch and IO chiplet programs targeting AI and data center SoCs. Role spans system architecture through full-chip integration and convergence, focused on achieving PPA targets across multi-million gate designs.

Part of the CSG Data Center team working on Qualcomm's rack-scale Agentic AI platform (Dragonfly); expected to coordinate cross-IP dependencies, synthesis convergence, and timing closure while mentoring engineering teams.

Experience Level

Senior (Director). The role expects extensive industry experience — the posting indicates senior-level candidates with long track records (guidance includes 18+ years of IP/SoC design and micro-architecture experience and relevant management experience).

Responsibilities

Lead SoC definition and delivery across architecture, RTL, verification, and physical implementation.

• Define, evaluate, and defend architectural and micro-architectural trade-offs for SoC-level designs.
• Drive milestone discipline across design, verification, synthesis, and physical implementation teams.
• Orchestrate cross-IP dependencies and resolve integration friction.
• Guide synthesis convergence and timing-closure strategies to meet constrained PPA targets.
• Oversee multi-million gate integration and full-chip convergence efforts.
• Mentor engineers on design-for-convergence, topology, buffering, clock domain strategy, and protocol partitioning.
• Provide hands-on RTL direction and review, including Verilog-based design practices.

Requirements

Required technical skills and demonstrated domain experience.

• Extensive IP/SoC design and micro-architecture experience (posting indicates senior candidates with long industry experience; see Education Requirements for degree-related years).
• Proven digital design and RTL development skills, including Verilog coding.
• Experience with SoC integration, synthesis convergence, and timing closure at advanced technology nodes.
• Experience in high-bandwidth data processing, low-latency transport, and energy-efficient data movement.
• Familiarity with Ethernet switch and IO chiplet architectures and related protocol partitioning.
• Demonstrated leadership: ability to lead cross-functional teams and mentor engineers through full design convergence cycles.
• Strong problem-solving and decision-making in areas where architecture choices impact physical implementation feasibility.
• Nice-to-have: prior work on data-center scale SoCs or rack-scale AI platforms and experience optimizing for throughput, latency, and energy.

Education Requirements

Degree and equivalent-experience language found in source: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field (with guidance such as 8+ years of hardware engineering experience); OR Master's degree in those fields (with guidance such as 7+ years); OR PhD in those fields (with guidance such as 6+ years). The posting also states a preference for Bachelor of Engineering as minimum, Masters preferred, and PhD candidates are welcome; it also references very senior experience levels (e.g., 18+ years of relevant IP/SoC experience and ~5+ years of relevant management experience). Equivalent practical experience is implied where degree+years alternatives are listed.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.