RTL Design (DDR) - Sr Lead Engineer

Job Title

RTL Design (DDR) - Sr Lead Engineer

Role Summary

Senior RTL design engineer responsible for micro-architecture and RTL development for DDR and related subsystems within Qualcomm's hardware engineering organization. The role focuses on front-end RTL implementation, validation for lint/CDC/DFT rules, timing closure, low-power design, and subsystem/SoC integration and debug.

Works closely with verification, physical design, and cross-functional teams to deliver production-ready silicon and support performance and post-integration debug activities.

Experience Level

Senior - typical 5–12 years of ASIC/RTL design experience; preferred 8+ years for lead roles.

Responsibilities

Primary responsibilities include RTL and micro-architecture development, validation, and cross-team integration.

• Develop micro-architecture and RTL; ensure compliance with lint, CDC, DFT and low-power rules.
• Collaborate with functional verification to create test plans and debug waveforms at core, subsystem, and SoC levels.
• Develop timing constraints and participate in timing closure activities.
• Write and validate UPF, perform power-aware equivalence checks, and run low-power verification flows.
• Support performance analysis and resolve performance bottlenecks.
• Provide integration and chip-level debug support during subsystem and SoC bring-up; support post-silicon debug when required.
• Plan and execute complex hardware simulations and analyses; produce technical documentation and provide guidance to less-experienced engineers.

Requirements

Key technical skills and experience required or strongly preferred for the role.

• Must-have: Strong RTL design and micro-architecture experience with ASIC flows (synthesis, DFT, functional verification, STA).
• Must-have: Hands-on experience with multi-clock designs and asynchronous interfaces.
• Must-have: Experience with front-end validation flows (lint, CDC analysis, low-power checks) and constraint development for timing closure.
• Must-have: Practical experience with UPF and power-aware equivalence or similar low-power design methodologies.
• Must-have: Strong communication skills and experience collaborating with global, cross-functional teams.
• Nice-to-have: Familiarity with DDR families and generations (LP/PC, DDR2/3/4/5/6) and common interconnect protocols (AHB/AXI/ACE/CHI).
• Nice-to-have: Post-silicon bring-up and debug experience.
• Nice-to-have: Background in circuit-level design, schematic capture, simulation, or use of lab measurement instruments is a plus.

Education Requirements

Qualifications cited: Bachelor's (BTech/Bachelor's) in Computer Science, Electrical/Electronics Engineering, or related engineering field; Master's (MTech/MS) or PhD in similar fields are also listed. The posting allows equivalent practical experience in lieu of degree (e.g., Bachelor's +4 years, Master's +3 years, PhD +2 years). A Master’s degree is listed as preferred.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.