RISCV CPU Design Verification Staff Engineer
QualcommJob Title
RISCV CPU Design Verification Staff Engineer
Role Summary
Staff-level design verification engineer responsible for verifying high-performance, low-power RISC-V CPU cores and related SoC features. The role sits in the hardware engineering organization in Bangalore and works across architecture, design, software, emulation and silicon teams to validate CPU functionality and power-management behavior.
Experience Level
Senior level. The listing targets experienced engineers; the role expects broadly 8+ years of relevant CPU or hardware verification experience (the posting also lists alternative minimums tied to degree level).
Responsibilities
Primary responsibilities include verification planning, execution, and debug for CPU units and system-level use cases.
- Develop and execute verification plans for CPU units and features.
- Implement and run simulation and formal verification tests; develop testbench components such as checkers, assertions, and stimulus generators.
- Create assembly- and C-language tests to validate CPU architecture and microarchitecture behaviors.
- Integrate and validate use cases with architects, design, software, and SoC teams.
- Enable and execute verification on emulation and FPGA platforms; work with emulation teams to debug failures.
- Debug and triage failures across simulation, emulation, and silicon bring-up.
Requirements
Must-have technical skills and experience; preferred items listed separately.
- Extensive experience in CPU design verification, preferably for high-performance or low-power CPU designs (RISC-V experience strongly preferred).
- Hands-on with simulation environments and formal verification methodologies.
- Proficient in SystemVerilog/Verilog and verification methodologies (UVM-style experience implied).
- Proficient in C/C++ and scripting for test development and infrastructure automation.
- Ability to write assembly and C tests targeting CPU architecture validation.
- Experience with emulation and FPGA-based verification platforms.
- Practical experience debugging complex failures across simulation, emulation, and silicon.
- Experience verifying power-management features (clock gating, power gating, UPF, DVFS/DCVS) is required.
Nice-to-have:
- Knowledge of CPU architectures and industry experience with x86/ARM/MIPS/POWER/RISC-V.
- Experience with advanced verification techniques (formal methods, assertions) and DFT/structural debug (JTAG, IEEE1500, MBIST, scan/memory dump).
Education Requirements
Degree requirements stated in the posting: Bachelor's (Computer Science, Electrical/Electronics Engineering, Engineering or related) with 4+ years experience; OR Master's in those fields with 3+ years; OR PhD in those fields with 2+ years. The posting also references BE/BTech in CS/EE (with senior experience expectation).
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
