RISC-V Infra System IP Design - Senior/Lead/Staff Engineer

Job Title

RISC-V Infra System IP Design - Senior/Lead/Staff Engineer

Role Summary

Design and deliver system IP and subsystems for RISC-V infrastructure within the Hardware Engineering organization. The role focuses on RTL and micro-architecture for SoC/IP, driving front-end design milestones and collaborating with global design, verification and physical implementation teams.

Experience Level

Senior-level. Typical experience range cited in the posting is approximately 3–15 years in IP/Sub System/SoC RTL design; specific minimum years vary by academic qualification (see Education Requirements).

Responsibilities

Key responsibilities include design, delivery and cross-team coordination for system IP and SoC front-end development.

• Architect and implement RTL for system IP and subsystems (SoC/IP level).
• Define and drive micro-architecture and interface with verification and physical teams.
• Work with bus protocols and interconnects (CHI/AHB/AXI/ACE/ACE-Lite) in system designs.
• Plan, track and manage front-end design dependencies and schedule across the SoC.
• Drive project milestones across design, verification and physical implementation phases.
• Support synthesis, timing-closure activities and silicon debug convergence.
• Communicate and collaborate with a large, geographically distributed engineering organization.

Requirements

Required technical skills and experience (degree details are listed separately under Education Requirements).

• Proven experience in IP/Sub System/SoC RTL design and micro-architecture.
• Strong Verilog/SystemVerilog RTL development and VLSI digital design flow knowledge.
• Familiarity with bus protocols and interconnect concepts (CHI, AHB, AXI, ACE, ACE-Lite).
• Working knowledge of system architectures (RISC-V and ARM), memory management and virtualization concepts.
• Understanding of multi-core ARMv8/v9 CPU architecture and coherency protocols.
• Experience with lint, CDC, PLDRC, synthesis, DFT, verification, formal verification and silicon debug.
• Practical understanding of design convergence from architecture and micro-architecture through verification and timing closure.
• Effective communication and collaboration skills for cross-functional, global teams.
• Nice-to-have: scripting for automation (Python or Perl) and familiarity with Gen AI tools; power-management fundamentals.

Education Requirements

Degree requirements vary by seniority: Bachelor's, Master’s or PhD in Electronics/Electrical Engineering, Computer Science, VLSI/Microelectronics or a related technical field. The posting lists example minimums by degree: Bachelor's (approximately 2–4+ years applicable experience), Master’s (approximately 1–3+ years), PhD (approximately 0–2+ years) depending on the specific qualification path.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.