RISC-V CPU Systems Architecture/RTL Engineer — Senior

Job Title

RISC-V CPU Systems Architecture/RTL Engineer — Senior

Role Summary

Work on RISC-V CPU system architecture and RTL for high-performance, low-power devices. Responsible for microarchitecture definition and RTL implementation of CPU system features such as timers, interrupts, power management, debug/trace, and configuration protocols. Collaborate with modeling, verification, software, firmware, and physical design teams to deliver CPU subsystems.

Experience Level

Senior-level. Typically 10+ years of relevant CPU RTL or microarchitecture engineering experience; senior role with substantial ownership of architecture and RTL delivery.

Responsibilities

Primary responsibilities include:

• Define high-level architecture and microarchitecture specifications for CPU system features.
• Design and implement RTL for system features; meet power, performance, area, and timing goals.
• Collaborate with CPU modeling and verification teams to explore performance and power optimizations and support verification strategies.
• Work with physical design, software, firmware, and platform teams to validate timing, power, reliability, testability, and system integration.
• Define and develop debug, trace, and telemetry features; support system-level debug and bring-up.

Requirements

Must-have skills and experience:

• Deep knowledge of microprocessor/system architecture and CPU system features (timers, interrupt controllers, configuration access, RAS/safety mechanisms, telemetry).
• Strong expertise in power management for high-performance systems (active and idle strategies, clock/limit architecture).
• Experience defining and developing debug/trace features, scan-dump and memory dump mechanisms.
• Proficiency in RTL coding (Verilog and/or VHDL) and use of simulators and waveform debugging tools.
• Solid understanding of logic design, timing closure, and power implications.
• Excellent technical writing and verbal communication skills.
• Ability to collaborate across cross-functional teams and to translate architecture into RTL implementation.

Nice-to-have:

• Familiarity with RISC-V ISA and CPU microarchitecture techniques.
• Experience with scripting (Python, Perl) for automation or modeling.
• Background in high-performance CPU design trade-offs and low-power microarchitecture techniques.

Education Requirements

Degrees: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields; postings reference a Master's preference. The posting also allows equivalent practical experience in lieu of a degree under specified experience combinations.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.