RISC-V CPU Design Verification Principal Manager/Engineer

Job Title

RISC-V CPU Design Verification Principal Manager/Engineer

Role Summary

Lead verification of high-performance, low-power RISC-V CPU designs within the Hardware Engineering team in Bangalore. Plan and execute verification strategies, build testbenches and validation environments, and collaborate with architecture, design, software and SoC teams to ensure functional and power-management correctness.

Experience Level

Senior-level role. Typical experience guidance in the posting indicates mid-to-senior experience (see Education Requirements for degree-to-years mapping).

Responsibilities

Primary responsibilities include:

• Develop and execute verification plans for CPU units and features.
• Create and maintain testbenches: checkers, assertions, and stimulus generators.
• Use simulation and formal verification methodologies to validate designs.
• Implement assembly and C tests to verify CPU architecture and micro-architecture.
• Work with architects, designers, software and SoC teams to validate system-level use cases.
• Enable and run verification on emulation and FPGA platforms; collaborate with emulation teams.
• Debug and triage failures in simulation, emulation and silicon; root-cause verification gaps.
• Drive verification of power-management features and ensure coverage for low-power modes.

Requirements

Must-have skills and experience:

• Proven experience in CPU design verification, preferably for high-performance or low-power CPUs.
• Hands-on experience with simulation flows and formal verification techniques; ability to develop assertions and formal checks.
• Experience building testbenches and verification components (checkers, stimulus generators).
• Experience implementing assembly and C tests for CPU verification.
• Proficiency in C/C++ and scripting languages; familiarity with Verilog/SystemVerilog or similar HDLs.
• Practical understanding of CPU architectures and micro-architectures; ability to work with architects and system teams.
• Experience enabling verification on emulators and FPGA platforms; debug across simulation/emulation/silicon.
• Experience verifying power-management features (clock gating, power gating, UPF, DVFS/DCVS, throttling) is required.

Nice-to-have:

• Industry experience with CPU architectures such as x86, ARM, MIPS, RISC-V, or POWER.
• Experience with DFT and structural debug methodologies (JTAG, IEEE1500, MBIST, scan/memory dump).
• Deeper formal verification expertise and coverage-driven verification experience.

Education Requirements

Posting lists degree-to-experience mappings: Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field with 8+ years of relevant experience; OR Master's degree in those fields with 7+ years; OR PhD with 6+ years. The posting also references BE/BTech in CS/EE with 4+ years of experience. Fields mentioned: Computer Science, Electrical/Electronics Engineering, Engineering, or related technical fields.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.