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RFIC Layout Engineer

Apple
September 14, 2026
Full-time
On-site
Irvine, California, United States
$118,019 - $207,100 USD yearly
Physical Design Jobs, Level - Mid-Career

Job Title

RFIC Layout Engineer

Role Summary

Design and integrate transistor-level and top-level layout for RF and analog blocks within Apple’s wireless SoC organization. Collaborate with circuit designers, verification, and system teams to deliver manufacturable layouts that meet performance, reliability, and schedule targets.

Experience Level

Mid-level. No explicit years-of-experience requirement provided.

Responsibilities

Primary responsibilities include:

  • Detailed transistor-level layout of RF and analog circuit blocks (LNA, mixers, PLL/LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, bandgap/bias/LDO).
  • Block-level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking.
  • Co-work with designers on block-level and top-level floorplanning and integration.
  • Perform layout reviews focused on power/ground routing, electromigration, signal path integrity, differential and IQ matching, and signal coupling.
  • Top-level layout integration, verification, and schedule management to meet project milestones.
  • Participate in cross-functional reviews and coordinate with verification, test, and system teams.

Requirements

Must-have and preferred skills:

Must-have:

  • Demonstrated experience with transistor-level RF/analog layout and top-level integration.
  • Understanding of RC delay, electromigration, and coupling; ability to recognize failure-prone circuit and layout structures and work with designers to resolve them.
  • Good communication skills and ability to work effectively with multi-functional teams.

Nice-to-have:

  • Experience in custom RF/analog layout for radio transceivers in deep sub-micron CMOS (16nm and below) and FinFET technologies.
  • Layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing; knowledge of guard rings, DNW, PN junctions, and process effects (e.g., LOD, WPE).
  • High proficiency interpreting Calibre DRC/ERC/LVS in FinFET process flows.
  • Capability to lead or mentor other layout engineers for top-level integration.
  • Scripting skills (Perl or SKILL) and extensive experience with Cadence layout tools.

Education Requirements

Bachelor's degree required. Field of study not specified.


About the Company

Company: Apple

Headquarters: Cupertino, California, United States

Apple is a multinational technology company that designs, manufactures, and sells consumer electronics, software, and online services. Known for its innovative products such as the iPhone, Mac computers, and iPad, Apple emphasizes a strong commitment to high-quality design and user experience.

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Date Posted: 2026-09-11