RET Layout/Mask Engineer

Job Title

RET Layout/Mask Engineer

Role Summary

The RET Layout/Mask Engineer designs and implements layouts used for lithography, OPC model calibration, reticle measurement, and mask evaluation for advanced process technologies (28nm). The role works within the Advanced Technology Development (ATD) organization and interfaces with process engineering, integration, PDK, RET/OPC teams, and fabs to make process monitoring and OPC development production-ready.

Experience Level

Mid-level. The posting specifies 5+ years of experience in Layout/Mask design.

Responsibilities

Primary responsibilities focus on creating and automating layouts to support lithography, OPC, and reticle measurement across technologies and fabs.

• Create layouts for setup, evaluation, and monitoring of lithography and etch wafer processes.
• Collaborate with process engineering and integration teams to determine layout specifications and measurement coordinates.
• Develop layouts for OPC development and model calibration, including test reticles and scribe modules.
• Define layout placement rules with RET, scribe, and design teams; maintain measurement coordinate lists.
• Create layouts for reticle measurement and disposition in coordination with PDK teams.
• Develop and implement automation to produce and manage layouts.
• Support multiple fabs and technologies as required.

Requirements

Must-have technical skills and experience. Preferred items are listed separately.

• Minimum: 5+ years relevant experience in layout or mask design (industry experience preferred).
• Proficiency with EDA layout tools (Cadence suite, Synopsys, or equivalent).
• Scripting experience (Python, SKILL, Perl, or similar) for layout automation.
• Experience creating layouts used for lithography/OPC calibration, test reticles, and process monitoring.
• Ability to collaborate across process, integration, RET/OPC, and PDK teams.

Preferred:

• Hands-on design or PDK development experience at a semiconductor company.
• Strong lithography knowledge and OPC experience.
• Experience with PG flows.
• Strong analytical and communication skills for cross-team collaboration.

Education Requirements

Posting lists a Bachelor's degree in Electrical Engineering, Physics, Computer Science, Chemistry, or a related technical field as the minimum educational background; the job information also indicates a Master's degree level. The posting does not explicitly state whether equivalent practical experience can substitute for a degree.

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.