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Research Intern - Loop Engineering

SK hynix America
October 7, 2026
Internship
On-site
San Jose, California, United States
$35 - $45 USD hourly
EDA Jobs, Level - Entry or Early Career

Job Title

Research Intern - Loop Engineering

Role Summary

Research intern working with a full-time researcher to build, extend, and evaluate closed-loop hardware/software co-design flows for SoC problems. The role focuses on implementing AI-assisted design loops, running experiments, and producing reproducible results and a short report with recommendations.

6-month, full-time (40 hours/week) onsite internship in San Jose starting immediately (September/October 2026).

Experience Level

Entry-level (Internship). Targets students or early-career researchers; no specific years-of-experience required.

Responsibilities

Primary responsibilities include designing, implementing, and evaluating co-design loops and documenting findings.

  • Define the structure of a design loop: steps, feedback signals, and how search/verification/physical results inform iterations.
  • Implement loops using languages and tools such as Chisel and XLS along with simulation, build, and physical-design tools.
  • Apply loops to SoC problems (microarchitectural exploration, RTL implementation and verification, or PPA optimization).
  • Compare loop variants on design quality, search cost, reproducibility, reuse, and failure diagnosis.
  • Make the loop rerunnable with clear interfaces, caching, regression checks, and report generation.

Requirements

Must-have technical skills and logistical availability.

  • Coursework or project experience in loop engineering, computer architecture, digital design, VLSI, or electronic design automation.
  • Fluent in Python and comfortable reading and modifying an existing codebase.
  • Ability to define a scoped research question, track experiments, and explain results clearly.
  • Available to work onsite in San Jose 40 hours/week for a 6-month internship starting immediately (September/October 2026).

Nice-to-have:

  • Exposure to RTL (Verilog, SystemVerilog, Chisel, or XLS) or SoC design frameworks.
  • Experience with architecture simulators or RTL simulation.
  • Familiarity with AI-assisted hardware/software co-design frameworks (e.g., CHIA) or scripted DSE/verification flows.

Education Requirements

Progress toward a bachelor’s, master’s, or Ph.D. in electrical engineering, computer engineering, computer science, or a related field; relevant coursework or project experience in the listed technical areas is expected.


About the Company

Company: SK hynix America

Headquarters: Icheon, South Korea

U.S. subsidiary of SK hynix, a global semiconductor company specializing in DRAM and NAND flash memory and related memory solutions for mobile devices, data centers, and consumer electronics. Focuses on advanced memory technologies, AI applications, and high-performance storage.

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Date Posted: 2026-10-07