Research Engineer - Mid-Training

Job Title

Research Engineer - Mid-Training

Role Summary

Train and refine frontier machine learning models to become domain experts in semiconductor design and verification. Build data generation, distillation, evaluation, and continual-learning pipelines that enable model-driven chip design and automated verification.

Work within a cross-functional research and engineering team alongside hardware engineers, reinforcement-learning researchers, verification specialists, and compute engineers to scale training and evaluation across large compute fleets.

Experience Level

Mid-level (mid-career). No explicit years-of-experience specified.

Responsibilities

Contribute to model training, data pipelines, evaluation, and scaling infrastructure focused on semiconductor design and verification.

• Train LLMs and foundation models on semiconductor design and verification corpora (RTL, netlists, PDKs, simulation logs).
• Design and implement methods to generate and curate large-scale synthetic design data (RTL variants, testbenches, verification traces).
• Develop model distillation and continual-learning workflows to keep models current at scale.
• Build evaluations that correlate model outputs with downstream design metrics (timing closure, power, area, verification coverage).
• Collaborate with hardware, verification, RL, and compute teams to integrate models into design and RL environments.
• Optimize compute budgets and training pipelines for chip-design-specific workloads; scale training across large GPU fleets.
• Implement high-performance analysis and tooling to study how data and simulation affect model behavior and design outcomes.

Requirements

Key technical skills and domain experience required or strongly preferred.

• Must-have: Experience training LLMs or foundation models, preferably on semiconductor design/verification data such as RTL, netlists, PDKs, or simulation logs.
• Must-have: Experience generating large-scale synthetic design data and building evals tied to hardware design metrics.
• Must-have: Practical experience optimizing compute budgets and scaling training for domain-specific workloads; familiarity with distributed training concepts.
• Must-have: Strong software engineering skills for building performant tooling and data pipelines.
• Nice-to-have: Experience with model distillation, continual learning, reinforcement learning integration, or semiconductor verification methodologies and metrics.
• Nice-to-have: Familiarity with GPU cluster orchestration and common ML frameworks for large-scale training and inference.

Education Requirements

Not specified.

About the Company

Company: Voltai

Headquarters: Palo Alto, CA, United States

Voltai develops AI-driven world models and agents to design, evaluate, and optimize physical systems—focusing on hardware, electronics, and semiconductors to enable AI-led hardware co-design, performance modeling, and cross-domain optimization.