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R&D Staff Engineer β€” Formality Team

Synopsys
June 10, 2026
Full-time
On-site
Bengaluru, Karnataka, India
EDA Jobs, Level - Senior

Job Title

R&D Staff Engineer β€” Formality Team

Role Summary

As a senior R&D engineer on the Formality team you will design, implement, and own core infrastructure of the Formality formal equivalence checking engine. The role focuses on C++ systems engineering to improve runtime, memory, capacity, and scalability for large production designs.

Responsibilities include profiling production designs, driving performance optimizations, leading design reviews, and resolving complex customer escalations end-to-end.

Experience Level

Senior. Experience guidance: 5+ years (BE/B.Tech), 3+ years (MS), or 2+ years (PhD) of professional software development in large production C++ codebases.

Responsibilities

Primary responsibilities include:

  • Architect, develop, and own core Formality verification engine infrastructure and abstractions.
  • Profile production workloads and re-engineer hotspots to improve runtime, memory, and capacity.
  • Design and harden parallel architectures to scale equivalence checking on multi-core machines.
  • Own complex customer escalations: reproduce issues, root-cause, implement fixes, and add safeguards to prevent regressions.
  • Initiate and lead design reviews; raise code quality and unit-test coverage.
  • Collaborate across teams to enable abstractions and future capabilities.

Requirements

Must-have technical skills and demonstrated experience:

  • Proven experience developing large, production C++ codebases with module ownership and technical leadership.
  • Expert command of modern C++, the STL, templates, and performance-focused memory and lifetime management.
  • Strong fundamentals in data structures and algorithms (graphs, hash tables, trees, traversal, BDD) with applied experience.
  • Demonstrated ability to profile, diagnose, and optimize runtime, memory, and scalability for large workloads.
  • Working knowledge of HDLs (Verilog/SystemVerilog/VHDL) and digital design fundamentals; familiarity with synthesis or equivalence checking preferred.
  • Comfort with TCL, Python, and shell scripting for tooling and regressions.
  • Strong written and verbal communication; ability to lead technical discussions and mentor peers.
  • Exposure to AI-assisted developer tools (e.g., GitHub Copilot) and interest in modern developer productivity practices is a plus.

Education Requirements

BE/B.Tech in Computer Science, Electrical, or Electronics Engineering; OR MS or PhD in a related discipline. Equivalent practical experience is acceptable. The posting specifies experience guidance tied to degree: 5+ years (BE/B.Tech), 3+ years (MS), or 2+ years (PhD).


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-06-07