R&D Engineering Staff Engineer

Job Title

R&D Engineering Staff Engineer

Role Summary

Senior verification engineer responsible for designing and implementing verification environments for Silicon Lifecycle Management (SLM) products. Work within a multidisciplinary team to validate digital, analog, and mixed-signal IP and lifecycle management features used by semiconductor customers.

Primary activities include creating comprehensive test cases, performing root-cause analysis of failures, developing automated regression suites, and working directly with customers and internal teams to resolve verification issues.

Experience Level

Senior level. The posting specifies a minimum of 4 years of professional experience in design verification.

Responsibilities

Key responsibilities include verification development, debugging, automation, and customer-facing technical support.

• Design and implement verification environments and test cases for SLM products.
• Perform root-cause analysis on complex failures across digital, analog, and mixed-signal domains using simulation and waveform analysis.
• Develop and maintain automated regression suites to protect product quality as features evolve.
• Use EDA tools and Unix/Linux environments to run simulations and automate verification workflows.
• Collaborate with customers and internal teams to reproduce reported issues and verify fixes.
• Monitor SLM and 3D-IC standards and incorporate relevant practices into verification.

Requirements

Must-have technical skills and competencies; listed nice-to-have items separately.

• Proven proficiency with EDA tools and Unix/Linux for verification and simulation tasks.
• Strong analytical and systematic debugging skills with a track record of resolving complex technical issues.
• Experience developing and maintaining automated test and regression suites.
• Effective written and verbal communication skills in English for technical documentation and collaboration.
• Experience working across digital, analog, or mixed-signal verification workflows.
• Nice-to-have: familiarity with 3D-IC standards and advanced packaging verification methodologies.

Education Requirements

Bachelor's or Master’s degree in Computer Science, Electrical Engineering, or a related technical field. The posting also specifies a minimum of 4 years of professional experience in design verification.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.