R&D Engineering Staff Engineer

Job Title

R&D Engineering Staff Engineer

Role Summary

Design and deliver production RTL for complex SoC/ASIC blocks and own their integration through synthesis and handoff. Work with verification, physical design, and architecture teams to resolve functional, timing, and CDC issues.

The role focuses on front-end RTL development, SDC constraints, lint/CDC/synthesis debugging, and subsystem glue logic for multi-IP integrations in commercial silicon projects.

Experience Level

Senior — typically requires 5+ years of relevant industry experience (the posting notes equivalence such as a Master’s degree with 3+ years of experience).

Responsibilities

Key day-to-day responsibilities include implementing RTL, integrating IP, producing constraints, and preventing integration blockers.

• Design and implement production-grade RTL in Verilog/SystemVerilog for SoC and ASIC components.
• Integrate IP blocks into subsystems; implement glue logic and subsystem interfaces.
• Write SDC for synthesis and ensure constraints reflect timing intent.
• Run and debug lint, CDC, and synthesis checks; resolve issues using tools like SpyGlass, Fusion Compiler, and Encounter.
• Collaborate with verification, physical design, and architecture teams to close functional and structural issues.
• Participate in microarchitecture discussions and translate intent into RTL that meets performance, power, and area targets.
• Mentor and guide junior engineers on RTL quality, coding standards, and front-end best practices.

Requirements

Must-have technical skills and practical experience; listed nice-to-have items separately.

• Must-have: Hands-on experience in RTL design and SoC/ASIC integration with responsibility for blocks through synthesis.
• Must-have: Strong proficiency in Verilog and SystemVerilog for production RTL.
• Must-have: Solid understanding of digital design fundamentals, microarchitecture, and multi-clock SoC integration challenges.
• Must-have: Experience running lint and CDC analysis and working with synthesis flows; ability to debug synthesis issues and write effective SDC.
• Must-have: Proven ability to debug CDC and lint reports and prioritize real issues vs tool noise.
• Nice-to-have: Experience with high-speed interfaces (PCIe, USB, AXI, I2C, JTAG).
• Nice-to-have: Familiarity with low-power design techniques and scripting (Python, Tcl, Perl).
• Nice-to-have: Experience using AI-assisted coding tools (e.g., GitHub Copilot) to improve productivity.

Education Requirements

Bachelor's or Master’s degree in Electronics Engineering, Electrical Engineering, or a related technical field. The posting allows equivalent practical experience (example equivalence noted: Bachelor's/ Master's with 5+ years of experience, or Master’s with 3+ years).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.