R&D Engineering, Senior Engineer (C++/Verilog)

Job Title

R&D Engineering, Senior Engineer (C++/Verilog)

Role Summary

Senior verification engineer responsible for verifying and deploying hardware emulation models (Zebu) and supporting pre-silicon SoC bring-up and software development. The role is individual-contributor or technical-lead oriented and works with cross-functional teams to integrate emulation models with verification and software workflows.

Work focuses on bus-protocol emulation, model implementation in C++/RTL/SystemVerilog-DPI, and improving verification efficiency for complex SoCs.

Experience Level

Mid-level — typically 2–4 years of hands-on experience in emulation/simulation and verification.

Responsibilities

Primary responsibilities include:

• Verify and deploy emulation models for Zebu, with emphasis on bus protocols such as PCIe, USB, CSI and DSI.
• Implement and maintain models and test infrastructure in C++, RTL, and SystemVerilog (including DPI interfaces).
• Collaborate with SoC, firmware, and software teams to support pre-silicon bring-up and enable software development on emulation platforms.
• Create and optimize usage models, test applications, and workflows for emulation projects to improve turnaround and reuse.
• Perform verification and validation, debug integration issues, and ensure model quality and performance.
• Provide technical guidance and mentorship to junior engineers as needed.

Requirements

Key qualifications and skills.

• Must-have: Strong programming skills in C++ with solid OOP fundamentals; proficiency in SystemVerilog and Verilog; solid understanding of digital design concepts and verification methodologies; practical experience with hardware emulation, model deployment, and SoC bring-up in pre-silicon environments.
• Nice-to-have: Prior experience with Zebu or similar emulation platforms; familiarity with scripting (Perl, TCL); experience with simulation/debug tools such as VCS and Verdi; knowledge of protocols like ENET, HDMI, MIPI, AMBA, UART; exposure to FPGA flows (synthesis, place-and-route).
• Good verbal and written communication skills and ability to collaborate across functional teams.

Education Requirements

B.Tech or M.Tech in Electrical & Electronics Engineering (EEE), Electronics & Communication Engineering (ECE), Electronics & Telecommunication Engineering (ETE), VLSI or a closely related engineering field. The posting indicates a typical experience range of 2–4 years in emulation/simulation.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.