R&D Engineering Senior Engineer

Job Title

R&D Engineering Senior Engineer

Role Summary

Senior physical-design engineer focused on foundry enablement and advanced-node implementation using Synopsys Fusion Compiler and related signoff tools. The role supports foundry partners, internal enablement teams, and customers to deliver scalable place-and-route and 3DIC solutions that meet aggressive power, performance, and area (PPA) targets.

The position involves hands-on debugging of complex multi-corner, multi-mode designs, driving test-chip projects from RTL to GDS, and improving implementation flows and automation to accelerate customer tape-outs.

Experience Level

Senior - the job title indicates a senior role. The posting references at least 2+ years of hands-on physical design experience.

Responsibilities

Core day-to-day responsibilities include design implementation, debugging, and enabling foundry flows:

• Develop and optimize foundry implementation and 3DIC solutions using Fusion Compiler aligned with reference methodology and advanced-node requirements.
• Provide direct engineering support to foundry partners and customers on DTCO, PPA optimization, and test-chip bring-up.
• Debug complex place-and-route, timing, power, and physical verification issues across multi-corner, multi-mode designs using tools such as PrimeTime, StarRC, IC Validator, and RedHawk.
• Drive foundry test-chip projects from RTL to GDS, coordinating with advanced-node enablement teams and foundry process groups.
• Support field account and internal jumpstart teams to accelerate customer adoption of physical-design solutions.
• Collaborate with cross-functional engineering teams across geographies to resolve project issues and close PPA gaps.
• Identify and integrate productivity improvements and automation, including exploration of AI-assisted engineering tools.

Requirements

Required technical skills and demonstrable experience. Degree details are summarized separately under Education Requirements.

• Must-have: Proficiency in place-and-route methodology, hierarchical design, and timing signoff using Fusion Compiler or equivalent P&R tools.
• Must-have: Hands-on experience with signoff and extraction tools such as PrimeTime, StarRC, IC Validator (DRC/LVS) and RedHawk (power analysis).
• Must-have: Proven ability to debug complex implementation issues spanning timing closure, power integrity, and physical verification.
• Must-have: Experience on high-performance or low-power designs with a track record of contributing to PPA improvements and flow optimization.
• Must-have: Strong cross-team communication and ability to work across time zones with foundry and customer engineers.
• Nice-to-have: Real tape-out experience on SoC, CPU, or GPU projects.
• Nice-to-have: Exposure to AI-assisted engineering tools or automation frameworks (e.g., Cursor).

Education Requirements

Required: Bachelor's or Master's degree in Electrical Engineering. The posting also specifies 2+ years of hands-on experience in physical-design implementation. (No certifications or explicit "equivalent experience" language was provided.)

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.