R&D Engineering Senior Architect

Job Title

R&D Engineering Senior Architect

Role Summary

Senior software architect for Custom Compiler placement and routing infrastructure, focused on advanced process nodes (5nm, 3nm, 2nm, 14A). The role sets technical direction, designs layout automation features, and leads development for EDA tools used by custom/analog designers.

Experience Level

Senior — senior-level engineering role. The posting specifies 15+ years related experience with a Bachelor’s, or 13+ years with an advanced degree; broadly expects well over a decade of EDA tool development and architecture experience.

Responsibilities

Architect and deliver placement and routing infrastructure and layout automation for Custom Compiler; set direction for product evolution and mentor engineers.

• Architect and implement placement and routing systems for advanced GAA and FinFET nodes (5nm, 3nm, 2nm, 14A).
• Design layout automation features that improve designer productivity for custom/analog layouts.
• Define technical direction and operational specifications based on customer workflows and EDA ecosystem analysis.
• Research and develop algorithms and tools to remove bottlenecks in custom IC layout.
• Integrate tooling with internal IP teams and proliferate automation across design flows.
• Mentor and guide junior engineers on architecture, coding standards, and quality practices.
• Manage maintenance and evolution of existing toolsets, balancing stability with new feature development.

Requirements

Core technical skills and experience required for the role. Degree-specific requirements are summarized separately under Education Requirements.

Must-have

• Extensive experience building EDA software and production-grade tools for custom IC design.
• Hands-on experience with Custom Compiler or Cadence Virtuoso (development or power-user level).
• Deep expertise in placement and routing algorithms for analog, mixed-signal, or custom digital layouts.
• Proven ability to architect software systems that balance performance, maintainability, and extensibility in complex EDA environments.
• Direct experience with advanced process node constraints (7nm or below) and scaling issues.
• Ability to lead technical direction, present to senior leadership, and mentor engineering teams.

Nice-to-have

• Experience working directly with semiconductor IP teams or custom IC design groups.

Education Requirements

Required: Bachelor's degree with a minimum of 15 years of related experience, or an advanced degree (e.g., Master's, PhD) with a minimum of 13 years of related experience. Preferred fields: Computer Science, Electrical Engineering, or equivalent technical fields. The posting also allows equivalent practical experience in lieu of degree-based requirements.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.