R&D Engineering Scientist
SynopsysJob Title
R&D Engineering Scientist
Role Summary
Lead PHY/SerDes architecture for high-speed serial interfaces, translating protocol, channel, and system requirements into implementable block-level architectures and cross-functional specifications. Work with analog, digital, SI/PI, package, verification, and silicon-validation teams to meet power, performance, area, latency, and reliability targets.
Experience Level
Senior-level (experienced architect / technical leader). The posting describes an experienced architect but does not state explicit years of experience.
Responsibilities
Accountable for end-to-end PHY architecture, link performance, and cross-team alignment. Typical responsibilities include:
- Own PHY architecture decisions including protocols, data rates, BER, and PPA targets.
- Define data-path and clocking architectures: modulation, equalization, FEC placement, ADC-DSP, PLL, and CDR.
- Lead calibration and adaptation strategies across process, voltage, temperature, and channel conditions.
- Perform link budgeting and close budgets across transmitter, package, channel, and receiver.
- Allocate power, area, performance, and latency across analog, digital, and package components.
- Produce block specifications for engineering implementation and verification.
- Define architecture sign-off, modeling, observability, and silicon bring-up requirements (loopback, PRBS, eye scan, calibration access).
- Align standards, signal/power integrity, package, and program teams on guaranteed IP performance.
Requirements
Key technical must-haves and useful additional skills:
Must-have:
- Architectural experience with 112 Gb/s and 224 Gb/s PAM4 serial links.
- Expertise in link budgeting: insertion/return loss, crosstalk, jitter, BER, channel operating margin, and FEC coding gain.
- Deep knowledge of CTLE, FFE, DFE, ADC-DSP, PLL, CDR, adaptation, and calibration techniques.
- Experience with channel and behavioral modeling, process-corner analysis, and PPA tradeoffs across analog, digital, and package.
- Silicon bring-up and debug experience using PRBS, loopback, eye scan, and calibration capabilities.
- Demonstrated ability to write clear technical specifications and present architecture decisions to technical, program, and customer audiences.
Nice-to-have:
- Prior experience delivering PHY IP for advanced silicon applications and working with cross-functional program teams.
- Familiarity with advanced modeling tools and methods for SI/PI and package co-optimization.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
