R&D Engineering, Engineer

Job Title

R&D Engineering, Engineer

Role Summary

Work on backend software for emulation systems, focusing on partitioning algorithms for multi-FPGA ZeBu emulation compile flows. The role sits on an R&D team that collaborates with FPGA place-and-route and runtime teams to deliver scalable, timing-aware partitioning solutions for large SoC designs.

Experience Level

Mid-level (mid-career). Years of experience not specified.

Responsibilities

Core responsibilities include algorithm development, integration with backend systems, and cross-team validation.

• Develop and optimize multi-FPGA partitioning algorithms for the ZeBu emulation compile flow.
• Design timing-aware partitioning approaches that include critical-path timing in cost models and objectives.
• Account for clocking constraints (driver/clock-driven domains, multi-cycle paths) when assessing partition feasibility and quality.
• Improve partitioning engine robustness and reduce sensitivity to random initial solutions; implement better initial-solution strategies.
• Apply analytical partitioning and optimization techniques to improve stability, reproducibility, and partition quality.
• Implement constraint-aware partitioning for logic/memory resources, inter-FPGA connectivity, and timing-related constraints.
• Collaborate with FPGA P&R and runtime teams to validate partitioning and support platform sign-off.
• Analyze performance bottlenecks and implement scalable, maintainable C/C++ backend components on Linux.

Requirements

Must-have technical skills and competencies, plus preferred background items.

• Must-have: Strong foundation in algorithms and data structures, including graph/hypergraph partitioning.
• Must-have: Production C/C++ experience and performance-oriented development on Linux/Unix.
• Must-have: Knowledge of partitioning and optimization techniques (e.g., hMetis, multi-way partitioning, heuristic and analytical methods).
• Must-have: Strong problem-solving, debugging, and experimental evaluation skills.
• Preferred: Experience with scripting for tooling and automation (Python, Tcl) to support workflows and experiments.
• Preferred: Exposure to timing-aware optimization concepts and clocking/multi-cycle path reasoning.
• Preferred: Background in analytical optimization approaches for large-scale problems (spectral methods, eigenvector-based techniques, etc.).

Education Requirements

Bachelor's or master’s degree in Computer Science, Electrical Engineering, or a related field (explicitly listed in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.