R&D Engineer, IC Design 4
Front-end ASIC design and verification engineer responsible for architecture definition, RTL/logic design, synthesis, and verification of digital cores. Work focuses on achieving functional correctness and timing closure for high-frequency designs.
Collaborate with cross-functional teams including physical implementation, system architects, and verification to deliver robust, production-ready IP blocks.
Senior β typically 6β8+ years of relevant ASIC/SoC design experience (see Education Requirements for degree/experience guidance).
Primary duties include front-end implementation and verification of ASIC logic blocks and supporting handoff to downstream teams.
Concise list of required technical skills and useful tool experience.
Bachelor's or Masters in Electrical Engineering, Computer Engineering or a closely related technical field. The posting specifies a Bachelor's degree with ~8+ years of related experience or a Master's degree with ~6+ years of related experience; equivalent practical experience is acceptable.
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
