R&D Engineer IC Design 4

Job Title

R&D Engineer IC Design 4

Role Summary

Senior ASIC front-end design and verification engineer responsible for architecture, RTL design, synthesis, and verification of digital cores. Work within a SoC/ASIC R&D team to deliver synthesizable RTL, constraints, and verification artifacts to meet timing and functional requirements.

The role requires independent technical ownership of blocks and collaboration with physical design, verification, and system teams to achieve timing closure and production-ready deliverables.

Experience Level

Level - Senior. Typical guidance: experienced engineer (senior) with multi-year ASIC front-end design and verification experience; specific degree-based experience expectations are listed under Education Requirements.

Responsibilities

Primary responsibilities include front-end design, synthesis and verification tasks:

• Define block architecture and implement RTL based on system requirements.
• Create and maintain synthesis constraints and run synthesis flows.
• Develop and execute verification plans including simulation and formal verification.
• Perform timing analysis and work with physical design to achieve timing closure.
• Simulate, debug, and optimize RTL and gate-level netlists.
• Collaborate across teams (physical implementation, test, system teams) to integrate and deliver blocks.

Requirements

Must-have technical skills and experience:

• Strong front-end ASIC design and verification experience (RTL design, simulation, debug).
• Experience with synthesis tools (Synopsys Design Compiler / DC topo or Cadence RTL Compiler) and writing constraints.
• Timing analysis experience using Synopsys PrimeTime for high-frequency designs; familiarity with liberty (.lib) timing models.
• Experience with formal verification tools (e.g., Synopsys Formality, Cadence Conformal) and simulation-based verification flows.
• Proficiency in scripting (TCL, Perl) to automate flows and analysis.
• Familiarity with linting (Spyglass) and power analysis of RTL/gate-level netlists.
• Knowledge of DFT and scan methodology.
• Version control experience (SVN or Git).

Nice-to-have:

• Deep experience with high-frequency timing closure and low-power optimization techniques.
• Prior work on large SoC integration or complex IP blocks.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field — or equivalent practical experience. The posting specifies a Bachelor's degree with 8+ years of related experience, or a Master's degree with 6+ years of related experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.