R&D Engineer, IC Design 4

Job Title

R&D Engineer, IC Design 4

Role Summary

Front-end ASIC design and verification role focused on architecture definition, logic design, synthesis, and verification of digital cores. Work covers simulation, formal verification, timing analysis, and debug from RTL through gate-level timing closure.

The position collaborates with physical implementation, verification, and system teams to deliver production-quality RTL and meet high-frequency timing and testability targets.

Experience Level

Senior — typically 8+ years of relevant ASIC/front-end experience with a Bachelor's degree or 6+ years with a Master’s; equivalent practical experience may be acceptable.

Responsibilities

Main responsibilities include front-end design, synthesis, verification, and timing closure.

• Define architecture and design logic blocks from system requirements.
• Perform RTL design and debug using Verilog simulation.
• Develop synthesis flows and constraints; run synthesis with Synopsys Design Compiler or Cadence RTL Compiler.
• Perform static timing analysis and work toward timing closure using PrimeTime and LIB models.
• Execute formal verification and equivalence checking using tools such as Synopsys Formality or Cadence Conformal.
• Run linting and quality checks (e.g., Spyglass) and support power analysis of RTL and gate-level netlists.
• Implement DFT/scan methodology and support testability integration.
• Collaborate with physical implementation and verification teams to resolve issues and deliverable schedules.

Requirements

Must-have technical skills and practical experience.

• Strong RTL design and verification experience with Verilog/SystemVerilog and simulation/debug workflows.
• Experience with synthesis tools (Synopsys Design Compiler / Cadence RTL Compiler) and writing constraints.
• Static timing analysis experience with PrimeTime and working knowledge of liberty (LIB) timing models.
• Experience with formal verification/equivalence tools (e.g., Formality, Conformal).
• Proficiency in TCL and Perl scripting for automation and flow integration.
• Familiarity with lint tools (Spyglass), power analysis for RTL/gate-level, and DFT/scan methodology.
• Version control experience (SVN or Git) and ability to work independently and across teams.
• Ability to analyze timing from physical implementation and drive timing closure for high-frequency designs.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field; or equivalent practical experience. Typical experience guidance: Bachelor's +8 years or Master's +6 years of related ASIC/front-end design experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.