R&D Engineer IC Design 4
Front-end ASIC design and verification engineer responsible for architecture definition, RTL/logic design, synthesis, and verification of ASIC cores. Role includes using simulation and formal methods, performing timing analysis from physical implementation, and collaborating with physical design, architecture, and verification teams.
Senior-level. Role expects multiple years of ASIC design experience; the posting specifies experience ranges tied to degree level (see Education Requirements).
The core responsibilities focus on front-end design, synthesis, verification, timing analysis, and debugging.
Technical must-haves and tool experience required for the role.
BS or MS in Electrical Engineering or Computer Engineering (or equivalent). The posting specifies a Bachelor's degree with 8+ years of related experience, or a Master's degree with 6+ years of related experience; equivalent practical experience is acceptable per the original posting language.
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
