R&D Engineer, IC Design 4
Engineer responsible for front-end ASIC core design and verification, covering architecture definition, RTL design, synthesis, and verification using simulation and formal methods. The role supports timing closure for high-frequency designs and collaborates with physical implementation, verification, and system teams.
Senior. Typical experience guidance: Master's degree with 6+ years or Bachelor's degree with 8+ years of relevant ASIC design experience.
Core responsibilities focus on RTL implementation, synthesis, verification, and timing closure for ASIC cores.
Must-have technical skills and experience for successful performance in this role.
BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field β or equivalent practical experience. The posting specifies a Bachelor's degree with 8+ years of related experience, or a Master's degree with 6+ years of related experience.
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
