R&D Engineer IC Design 4

Job Title

R&D Engineer IC Design 4

Role Summary

Front-end ASIC design and verification engineer responsible for architecture definition, RTL/logic design, synthesis, and verification of ASIC cores. Works with implementation, verification and system teams to deliver timing-closed, verified RTL for high-frequency designs.

Role focuses on synthesis and timing closure, simulation and formal verification, and cross-team debug from RTL through gate-level.

Experience Level

Senior level. Hiring guidance provided in posting: Bachelor's degree with 8+ years related experience, or Master's degree with 6+ years related experience.

Responsibilities

Key responsibilities include translating system requirements into synthesizable RTL, ensuring design quality, and achieving timing closure.

• Define architecture and design logic blocks from system requirements.
• Perform RTL design and synthesis; develop and apply synthesis constraints.
• Run and analyze static timing reports from physical implementation to achieve timing closure.
• Perform design verification using simulation and formal verification methods.
• Simulate, debug, and validate designs using Verilog simulation environments.

Requirements

Must-have skills and tools for successful performance in the role.

• Must-have: Proven ASIC front-end design and verification experience (architecture, RTL/logic design, synthesis, verification).
• Must-have: Experience with synthesis tools (Synopsys Design Compiler / DC topo or Cadence RTL Compiler) and writing synthesis constraints.
• Must-have: Static timing analysis experience (Primetime) and familiarity with liberty (LIB) timing models.
• Must-have: Experience with simulation and formal verification tools and methodologies (e.g., Synopsys Formality, Cadence Conformal).
• Must-have: Strong RTL debug skills and experience with linting tools (e.g., Spyglass) and version control (SVN or Git).
• Must-have: Scripting experience (TCL and/or Perl) to automate flows.
• Nice-to-have: Experience with power analysis of RTL and gate-level netlists, DFT/scan methodology, and familiarity with gate-level verification flows.

Education Requirements

BS or MS in Electrical Engineering or Computer Engineering (posting specifies BS/MS in Electrical or Computer Engineering). Posting also allows equivalent practical experience and gives experience-based hiring guidance: Bachelor's +8+ years, or Master's +6+ years.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.