R&D Engineer IC Design 4
Front-end ASIC design engineer responsible for architecture, RTL logic design, synthesis, and verification of digital cores. The role requires hands-on implementation, simulation and formal verification, timing analysis, and cross-team collaboration to deliver production-quality cores.
Senior level. The posting specifies experience expectations (see Education Requirements) indicating a senior engineer with multiple years of ASIC design experience.
Key responsibilities include design, verification, and timing closure for digital ASIC blocks.
Must-have skills and tools for the role; degree and years-of-experience are listed under Education Requirements.
BS or MS in Electrical Engineering or Computer Engineering (or equivalent). The posting specifies a Bachelor's degree with 8+ years of related experience, or a Master's degree with 6+ years of related experience; equivalent practical experience is acceptable.
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
