R&D Engineer

Job Title

R&D Engineer

Role Summary

Join the Top-Level-Route (TLR) R&D team to lead place-and-route, physical verification, and post-tapeout integrity checks for complex SoC designs. The role focuses on congestion/routability, timing closure, and chip finishing towards tapeout.

Experience Level

Mid-level (guidance: 4–10 years of relevant VLSI/physical design experience).

Responsibilities

Primary responsibilities include ensuring physical design quality, meeting timing and power integrity requirements, and supporting tapeout activities.

• Execute place-and-route flows, clock tree synthesis (CTS), and routability/congestion analysis.
• Perform physical verification tasks: DRC, LVS, antenna checks, layout vs. schematic and chip finishing for tapeout.
• Integrate analog blocks and ensure RC/timing requirements for special/manual signals.
• Run post-layout signoff flows and integrity checks; manage post-tapeout eJob view and releases.
• Implement timing ECOs and fixes for IR drop, EM, and signal integrity issues.
• Extract/verify SPEF, perform noise analysis, and apply EM fixes.
• Collaborate with cross-functional team members to meet product development milestones and communicate technical status.
• Adapt to new responsibilities and evolving tool/technology requirements.

Requirements

Required technical skills and experience for successful performance in this role.

• 4–10 years of experience in VLSI physical design or related CAD/implementation roles.
• Hands-on experience with place-and-route and CTS; strong routability and congestion analysis skills.
• Solid experience with physical verification concepts: DRC, LVS, antenna, and chip finishing for tapeout.
• Proficient scripting skills (Perl, TCL) for automation and flow development.
• Practical experience implementing timing ECOs, IR-drop mitigation, SPEF extraction, and signal/EM fix implementation.
• Familiarity with signoff and verification tools and flows; ability to run and interpret post-layout checks.
• Effective communication and teamwork skills to coordinate with designers and verification engineers.

Nice-to-have

• Experience with Cadence Innovus and Mentor/Siemens Calibre (or equivalent) signoff tools.
• Knowledge of STA, PTSI, DFY, ERC, ESD latchup considerations, and VLSI fabrication process details.

Education Requirements

Not specified.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.