PST Validation Engineer

Job Title

PST Validation Engineer

Role Summary

Post-silicon validation and emulation engineer responsible for silicon bring-up, system-level characterization, debug, emulation management, and automation for SoC IPs. Works with cross-functional teams (CAD, RTL, design, software) to validate performance, power, and stability across process, voltage, and temperature corners.

Experience Level

Entry-level. Typical experience guidance in the posting: Bachelor's + 2+ years relevant ASIC/validation experience; Master's + 1+ year; or PhD.

Responsibilities

Primary day-to-day responsibilities include:

• Perform silicon bring-up and system-level measurements (Vmin/Fmax, power, thermal) across PVTs and SoC IPs and correlate results.
• Debug low-level software and hardware issues using JTAG, kernel debuggers, and other debug tools.
• Manage emulation builds, run tests on emulation platforms, identify failures and performance issues, and drive fixes with CAD, RTL, and design teams.
• Automate validation flows, data collection, and analysis using Python or similar scripting languages.
• Develop and maintain testbench infrastructure for CPU/SoC emulation across platforms.
• Document results, communicate findings, and coordinate with cross-functional teams to meet deadlines.

Requirements

Must-have technical skills and experience (education details are in Education Requirements):

• Understanding of mobile SoC architecture (CPU, GPU, DDR, NOCs) and basic RTL familiarity.
• Knowledge of regression testing and PVT (process, voltage, temperature) testing and data analysis.
• Experience debugging low-level software/hardware issues and using hardware debug tools.
• Strong programming and scripting skills (C and Python preferred); experience automating flows and data analysis.
• Experience with emulation platforms and building/maintaining test infrastructure for CPU/SoC validation.
• Good written and verbal communication, multitasking, and ability to work to deadlines.
• Ability to collaborate with CAD, RTL, and design teams to resolve failures and performance issues.

Nice-to-have:

• Familiarity with Lauterbach Trace32 or similar kernel/JTAG debuggers.
• Experience with architecture and design tools and design verification methods.
• Experience or interest in prompt engineering for tooling or automation workflows.

Education Requirements

Degrees and acceptable combinations stated in the posting: Bachelor's degree in Science, Engineering, or a related field (typically combined with 2+ years of ASIC design/verification/validation/integration experience); OR Master's degree in Science, Engineering, or related field (typically combined with 1+ year of relevant experience); OR PhD in Science, Engineering, or related field. Preferred fields mentioned include Electrical/Electronic Engineering, Computer Engineering, and Computer Science.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.