Product Power Engineer
SiFiveJob Title
Product Power Engineer
Role Summary
The Product Power Engineer will collect, analyze, and optimize power consumption across SiFive IP. The role works cross-functionally with architecture, RTL, implementation, and silicon teams to improve power models and drive power-efficient design decisions.
Experience Level
Mid-level — requires 5+ years of relevant experience in power benchmarking, analysis, and modeling.
Responsibilities
Primary responsibilities include:
- Collect and analyze IP power consumption data.
- Develop and validate power models correlated with RTL and silicon.
- Advise architecture and design teams on power-performance trade-offs.
- Optimize designs for power efficiency across architecture, logic, and circuit levels.
- Innovate and improve power analysis flows, methodology, and tooling.
Requirements
Must-have:
- 5+ years of experience in power benchmarking, analysis, and modeling.
- Experience evaluating power impacts at architecture, logic, and circuit levels.
- Strong knowledge of high-performance out-of-order CPU architecture.
- Experience guiding trade-offs between performance and power to reach optimal designs.
- Experience with ASIC power analysis and optimization.
- Self-starter with strong problem-solving skills.
Nice-to-have:
- Hands-on experience in hardware (RTL, implementation, verification/validation, backend, FPGA flows) or software development.
Education Requirements
MS or PhD in Computer Science or Computer Architecture.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
