Product Engineer II (DDR IP)

Job Title

Product Engineer II (DDR IP)

Role Summary

Mid-level product engineering role on the Memory IP team responsible for pre-sales engagement, post-sales technical support, and customer integration of high-performance memory PHY and controller IP (DDR/LPDDR/HBM/GDDR).

The engineer will be the primary technical interface between customers, Cadence R&D, and system validation teams, focusing on integration, verification, and troubleshooting of memory subsystems.

Experience Level

Mid-level. The role expects industry experience; the posting specifies a minimum of 2 years relevant experience for candidates with a B.S., or experience consistent with an M.S. level candidate.

Responsibilities

Primary responsibilities include customer integration support, internal QA, and technical problem resolution for memory subsystem products.

• Support pre-silicon integration, implementation, and usage of memory subsystem products (Controller + PHY).
• Perform internal system integration and QA testing for memory subsystems.
• Analyze and resolve complex subsystem application or implementation issues; provide technical guidance to customers.
• Support SOC integration and implementation reviews for memory PHY and controller IP.
• Assist customers with RTL and gate-level simulation flows to verify functionality.
• Support timing closure and other aspects of physical integration for customer designs.
• Participate in product documentation, customer checklists, and integration guides.
• Support post-silicon bringup and production test activities as needed.
• Provide prompt, thorough, and technically accurate responses to customer inquiries.
• Leverage AI-powered tools and analytics to improve productivity and extract actionable insights from data.

Requirements

Required technical skills and domain experience for successful performance in the role.

• Hands-on experience with DDR5/4/3, LPDDR5/4/3, HBM3, GDDR6 or similar memory IPs.
• Verilog RTL design and gate-level verification experience.
• Synthesis and static timing analysis (STA) experience; physical implementation/verification is a plus.
• Familiarity with industry-standard DFT flows and test methodologies.
• Familiarity with package and board design; ability to read schematics and participate in SI/PI reviews.
• Ability to collaborate with remote teams and manage multiple priorities; strong oral and written communication skills.
• Customer-facing experience, including debugging integration issues and supporting bringup or production testing.

Education Requirements

Required: B.S. in Electrical Engineering, Computer Engineering, or a similar technical degree with a minimum of 2 years relevant industry experience; OR M.S. in Electrical/Computer Engineering (or similar). Preferred: M.S. with 2+ years relevant industry experience. (Degree fields: Electrical Engineering, Computer Engineering or closely related technical fields.)

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.