Product Engineer II (DDR IP)

Job Title

Product Engineer II (DDR IP)

Role Summary

Product Engineer II on the Memory IP team supporting DDR/LPDDR/HBM/GDDR products. The role provides pre-sales engagement and post-sales technical support for memory PHY and controller IP, acting as the primary interface between customers, Cadence R&D, and system validation teams.

Location: Nanjing or Shanghai. The team focuses on IP integration, validation, and customer enablement for high-performance memory subsystems.

Experience Level

Mid-level — the position expects relevant industry experience (minimum ~2 years for candidates with a B.S.; M.S. also accepted).

Responsibilities

Provide technical support and enablement for memory subsystem IP across product lifecycle stages.

• Support pre-silicon integration and implementation of memory subsystem products (Controller + PHY).
• Assist internal system integration and QA testing for memory subsystems.
• Analyze and resolve complex application or implementation issues; provide technical guidance to customers.
• Participate in SOC integration and implementation reviews with customers.
• Assist customers with RTL and gate-level simulations to verify functionality.
• Support timing closure and other aspects of physical integration.
• Support post-silicon bring-up and production test activities as needed.
• Develop and refine product documentation, customer checklists, and integration guidance.
• Provide prompt, accurate responses to customer technical inquiries and collaborate with global teams.
• Use AI-powered tools and analytics to improve productivity and extract actionable insights from complex datasets.

Requirements

Must-have technical skills and experience for hands-on customer-facing engineering support.

• Practical experience with DDR5/4/3, LPDDR5/4/3, HBM3, GDDR6 or similar memory IPs.
• Verilog RTL design and gate-level verification experience.
• Synthesis and static timing analysis experience; physical implementation/verification is a plus.
• Familiarity with industry-standard DFT flows and test methodologies.
• Experience with package and board design; ability to read schematics and participate in SI/PI reviews.
• Strong customer-facing communication skills and ability to manage multiple priorities across distributed teams.
• Experience performing SOC integration reviews and delivering technical support to customers.

Nice-to-have:

• Experience with Memory PHY architectures and DSP-based designs.
• Experience with embedded microcontroller firmware for IP integration.

Education Requirements

Required: B.S. in Electrical or Computer Engineering (or similar) with a minimum of ~2 years of relevant industry experience, or an M.S. in Electrical or Computer Engineering (or similar). Preferred: M.S. with 2+ years of relevant industry experience. "Or similar degree" language is used in the source.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.