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Product Development Engineer - Scan Diagnostics

Intel Corporation
June 17, 2026
Full-time
Remote friendly (Santa Clara, California, United States)
Worldwide
$141,910 - $269,100 USD yearly
DFT Jobs, Level - Mid-Career

Job Title

Product Development Engineer - Scan Diagnostics

Role Summary

Responsible for enabling and supporting scan/chain diagnostics, post-silicon debug, and yield analysis to move integrated circuits from design to high-volume manufacturing. Work within cross-functional product and NPI teams and with external vendors to ensure diagnostic readiness and continuous yield improvement.

This role combines hands-on technical diagnostics, tool and flow development, and collaboration with Design, Yield Management, and Failure Analysis teams.

Experience Level

Mid-level. The posting requests a minimum of 4+ years of relevant experience in DFT, scan diagnostics enablement, post-Si diagnostics, yield analysis, or EDA tools.

Responsibilities

Key responsibilities include building diagnostic infrastructure, supporting production ramps, and improving yield through analysis and tooling.

  • Create, enable, and maintain scan/chain diagnosis infrastructure and processes for high-volume manufacturing products.
  • Perform fail-based and volume diagnostic analysis to drive yield improvement.
  • Develop and optimize tools, methods, and flows for Design for Test (DFT), diagnostics, and yield analysis.
  • Support CAD infrastructure and computational resources for diagnostics across product lines.
  • Collaborate with EDA vendors and external partners to adopt industry practices and toolchains.
  • Define and monitor DFX quality metrics (coverage, test cost, debuggability) from development through production ramp.
  • Facilitate knowledge transfer to Yield Management and Failure Analysis teams to maintain diagnostic readiness.
  • Work closely with Design and New Product Introduction teams to ensure diagnostic readiness for new products.

Requirements

Requirements are split into must-have and nice-to-have items.

Must-have:

  • 4+ years of experience in DFT, scan diagnostics enablement, post-Si diagnostics debug, yield analysis, and/or EDA tools.
  • Proficiency in at least one scripting language: Python, TCL, C-Shell, or PERL.
  • Experience conducting diagnostic and yield analysis to identify failure modes and improve yield.
  • Strong communication and teamwork skills.

Nice-to-have:

  • Experience with Siemens Tessent or similar test and yield analysis tools.
  • Experience with Synopsys Yield Explorer or similar tools.
  • Familiarity with SOC/IP DFT control architectures (e.g., JTAG, IJTAG, IEEE1500).
  • Background in custom or ASIC circuit design.

Education Requirements

Bachelor's degree in engineering or a related field is required. Master's degree or Ph.D. is preferred. (Source lists engineering or related technical fields.)


About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.

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Date Posted: 2026-06-15