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Principal VLSI/ ASIC Design Engineer

Hewlett Packard Enterprise
November 5, 2026
Full-time
Remote friendly (Sunnyvale, California, United States)
Worldwide
$181,000 - $367,000 USD yearly
VLSI Design Jobs, Level - Senior

Job Title

Principal VLSI/ ASIC Design Engineer

Role Summary

Lead architecture, RTL design, implementation, and analysis of complex VLSI components and SoC solutions for networking, compute, and related applications. Serve as a technical authority across product teams, influence architectural direction and roadmaps, and mentor engineering staff.

Experience Level

Senior - typically requires 9+ years of experience in ASIC, VLSI, SoC, or related hardware design.

Responsibilities

Accountable for driving ASIC design from early architecture through production readiness and for providing cross-functional technical leadership.

  • Lead early-stage ASIC architecture and microarchitecture exploration for complex SoC applications.
  • Define architectural approaches, implementation plans, and design methodologies aligned with product requirements.
  • Design, develop, and modify complex RTL blocks using industry-standard HDLs.
  • Drive RTL implementation through synthesis, timing closure, physical implementation support, and signoff.
  • Analyze tradeoffs across performance, power, area, scalability, reliability, and schedule.
  • Establish operating expectations via modeling, simulation, prototyping, and empirical evaluation.
  • Conduct design reviews and enforce architecture, implementation, and quality standards.
  • Create integration plans for new IP, tools, and design practices across products.
  • Collaborate with hardware, firmware, verification, physical design, software, manufacturing, and external partners.
  • Mentor engineers, provide technical guidance, and influence decisions across business units.

Requirements

Must-have technical skills and experience required to perform the role effectively.

  • Advanced knowledge of ASIC and VLSI design principles, digital logic, and SoC development.
  • Proven experience developing complex RTL using Verilog, SystemVerilog, or comparable HDLs.
  • Familiarity with full ASIC development flows: architecture, RTL coding, synthesis, timing analysis, and physical design interaction.
  • Experience with design modeling, simulation, performance analysis, and empirical evaluation methods.
  • Strong analytical and technical decision-making skills; ability to evaluate design alternatives and tradeoffs.
  • Experience defining or improving design methodologies, automation, and engineering practices.
  • Strong written and verbal communication skills; ability to present technical concepts to technical and executive audiences.
  • Proven ability to collaborate across distributed, cross-functional teams and to influence stakeholders without direct authority.

Nice-to-have (preferred)

  • Experience with networking ASICs, DPUs, switching, routing, packet-processing pipelines, or high-performance compute architectures.
  • Familiarity with formal verification, constrained-random verification, coverage methodologies, or verification planning.
  • Experience with low-power design, CDC/CDC handling, DFT, design-for-reuse, and high-speed interfaces.
  • Experience working with IP vendors, foundries, or outsourced development partners.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent practical experience may be considered.


About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.

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Date Posted: 2026-11-05