Principal Timing Signoff Engineer

Job Title

Principal Timing Signoff Engineer

Role Summary

Lead signoff methodology and timing closure efforts for Synopsys standard cell libraries used on advanced process nodes. The role owns timing signoff strategy, correlation between models, simulation and silicon, and delivery of scalable validation and QA infrastructure.

Work cross-functionally with characterization, CAD, modeling, EDA vendors, and foundry partners to ensure reliable timing prediction and successful deployment across customer tape-outs.

Experience Level

Senior - requires extensive experience; posting requests 15+ years of semiconductor industry experience in timing signoff, static timing analysis, and standard cell library development.

Responsibilities

Primary day-to-day responsibilities include:

• Define and own timing signoff methodology for standard cell libraries across advanced nodes (e.g., TSMC N3/N5/N7 and derivatives).
• Develop and validate multi-corner, multi-mode signoff flows for low-VDD, high-performance, and AI/compute SoCs accounting for variation, aging, and voltage drop.
• Perform correlation analysis between Liberty models, PrimeTime STA, SPICE simulations, parasitic extraction, and silicon measurements to improve timing prediction.
• Debug critical customer timing issues and drive root-cause analysis spanning characterization, PDKs, extraction, and EDA tool behavior.
• Build automation and QA infrastructure (Python, Tcl, Linux) to scale signoff validation across library releases.
• Create technical documentation, best practices, and deployment recommendations for internal teams and customers.
• Collaborate with foundries, EDA vendors, and characterization teams to influence methodology and resolve advanced-node timing challenges.
• Mentor senior engineers and technical leads on timing signoff and correlation techniques.

Requirements

Must-have skills and experience:

• 15+ years in the semiconductor industry with deep hands-on experience in timing signoff, STA, and standard cell library development.
• Recognized expertise in STA and signoff methodologies for advanced process nodes (experience with TSMC N7/N5/N3 or equivalent preferred).
• Proficiency with Synopsys PrimeTime, PrimeTime-SI, SiliconSmart or Liberate, and SPICE simulators (HSPICE, Spectre, FineSim).
• Strong knowledge of Liberty modeling, LVF, AOCV/POCV/SOCV, statistical timing, and variation-aware signoff techniques.
• Expert automation skills in Python and Tcl and experience building scalable validation and QA infrastructure on Linux.
• Proven ability to correlate STA, SPICE, extraction, and silicon data to close signoff gaps and resolve discrepancies.
• Demonstrated track record deploying signoff methodologies adopted across products or customers and presenting recommendations to senior technical audiences.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.