Principal Technical Engineer, 3rd Party IP Engineer

Job Title

Principal Technical Engineer, 3rd Party IP Engineer

Role Summary

Senior engineer on the Central Engineering 3rd-party IP management team responsible for integrating subcontracted memory and storage interface IP (DDR/LPDDR/GDDR/HBM/eMMC) into Marvell SoCs. The role covers IP evaluation, supplier management, core integration, test compliance and silicon validation across multiple product groups.

Expect cross-functional collaboration with IP providers, internal design centers, sales and customers; limited travel for post-silicon validation may be required.

Experience Level

Senior-level. Typical experience range indicated by the employer: 5–10 years with a Bachelor's or 3–5 years with an advanced degree; equivalent professional experience acceptable.

Responsibilities

Core responsibilities include managing 3rd-party memory/storage IP from procurement through silicon validation.

• Define IP requirements and acceptance criteria for SoC integration.
• Evaluate and validate competence of 3rd-party IP providers and oversee their deliverables.
• Manage IP development schedules, statements of work, and progress reviews with suppliers.
• Integrate cores into SoC designs; advise internal design centers and run joint design reviews with suppliers.
• Ensure technology, test and compliance requirements are met (timing, DRC/LVS, packaging, test vectors).
• Coordinate silicon bring-up, post-silicon validation and customer site activities; support limited travel.
• Drive supplier issue resolution using problem-reporting tools and 8D or equivalent processes.
• Support sales by translating customer requirements into IP capabilities and tradeoffs.

Requirements

Must-have technical skills and experience to perform the role.

• Deep understanding of DDR-family interfaces and related SoC PHY integration, timing and packaging challenges (DDR, LPDDR, GDDR, HBM, eMMC).
• Practical experience with ASIC design flow elements: logic synthesis, physical design, timing closure, DRC/LVS, formal and electrical checks.
• Knowledge of Design-for-Test: DFT insertion, test generation, scan and embedded core testing.
• Project and supplier management skills to lead 3rd-party developers and manage schedules and deliverables.
• Strong communication and customer-management skills; able to run technical reviews and coordinate multiple stakeholders.
• Willingness to travel occasionally for post-silicon validation.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering or related field (typical experience expectation: 5–10 years). Alternatively, a Master's degree or PhD in Computer Science, Electrical Engineering or related field with ~3–5 years of experience. Employer also accepts equivalent professional experience in lieu of a formal degree.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.