Principal System Hardware (SIPI) Engineer

Job Title

Principal System Hardware (SIPI) Engineer

Role Summary

Lead SI/PI engineering for high-speed SerDes SoC products, focusing on PCB, package, de‑embedded structures, and system-level interconnect and power distribution network design, characterization, and validation. Collaborate with packaging, layout, validation, product, and customer teams and mentor junior engineers.

Experience Level

Senior — requires 6+ years of industry experience in SI/PI, EMI, and high-speed design.

Responsibilities

Primary responsibilities:

• Define and lead SI/PI activities and analysis for PCBs, de‑embedded structures, and system interconnects.
• Work with PCB layout engineers and fabs to define layout guidelines and review/approve final Gerber files for fabrication.
• Develop and refine methodologies for modeling, simulation, and measurement correlation to minimize gaps between simulation and measurement.
• Drive innovation in I/O, channel, and PDN architectures to enable higher speeds, densities, and lower IR drop and power noise.
• Collaborate with packaging, system, and validation teams to define test fixtures for silicon characterization, debug, and system robustness testing.
• Mentor and coach engineers, providing technical guidance and fostering engineering best practices.
• Perform research in electromagnetic modeling, PDN optimization, and advanced packaging to support future product direction.
• Provide SI/PI expertise to customers to ensure product performance meets application requirements.

Requirements

Must-have:

• 6+ years industry experience in signal and power integrity (SI/PI), EMI, and high-speed design.
• Deep expertise in electromagnetic theory, transmission lines, RF concepts, and analog design principles.
• Strong background with high-speed SerDes architecture, link optimization, and standards (IEEE 802.3, OIF).
• Proficiency with SI/PI simulation and analysis tools (examples: HFSS, SIwave, ADS, HSPICE, Q3D).
• Practical PCB layout skills; ability to adjust/modify layouts during design optimization and to review final fabrication files.
• Experience using Vector Network Analyzers (VNA), probe stations, calibration, and measurement techniques.
• Proven technical leadership, cross-functional collaboration, and strong technical communication skills.

Nice-to-have:

• Experience in PDN optimization, advanced packaging, electromagnetic modeling, and measurement correlation.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or a related technical field.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.