Principal Subsystem Engineer (Design or DV)

Job Title

Principal Subsystem Engineer (Design or DV)

Role Summary

Join Microsoft SCHIE's AISoC team to lead design or design-verification (DV) efforts for memory and complex subsystems in high-performance AI SoCs, delivering IP and SoC from concept through silicon bring-up. The role is an individual contributor position focused on enabling Microsoft cloud infrastructure hardware.

Hybrid role: typically 3 days per week in-office in Mountain View. Travel is under 25%.

Experience Level

Senior. See Education Requirements for the formal degree and years-of-experience combinations used for minimum qualifications.

Responsibilities

Lead delivery of subsystem IP and SoC functionality, collaborate across disciplines, and provide technical leadership and mentorship.

• Lead design or DV for memory subsystems and other complex subsystems (e.g., PCIe, HBM, NoC, DMA engines).
• Deliver high-performance IP and SoC components addressing bandwidth, latency, utilization, and power trade-offs.
• Develop microarchitecture specs, RTL (Verilog/SystemVerilog) implementation, synthesis/timing constraints and PPA tuning (Design) or develop UVM-based constrained-random testbenches, scoreboards, checkers, assertions and coverage closure (DV).
• Work with architecture, DFT, firmware, physical design, and post-silicon teams to debug system-level issues and drive silicon bring-up.
• Promote reuse across teams and mentor engineers; provide technical leadership on subsystem integration and verification strategies.

Requirements

Key must-haves and preferred qualifications. Degree and field details are in Education Requirements below.

• Must-have: Ability to pass Microsoft Cloud background check and required security screenings.
• Must-have: Eligibility to access export-controlled information; able to provide proof of citizenship or protected status as required for export-control assessment.
• Must-have: Experience debugging RTL in simulation and/or emulation environments and collaborating on design verification and CDC/lint closure.
• Preferred: Experience with DFT implementation and handoff to physical design, synthesis/timing optimization, and post-silicon debug.
• Preferred: Experience building verification environments (UVM), scripting (Python/Perl), formal property verification, and working across multiple product cycles to achieve coverage signoff.
• Preferred: Prior leadership of IP or subsystem projects (CPUs, VPUs, GPUs, DMA, tensor units) and experience on AI/ML SoCs.
• Travel: less than 25%.

Education Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 3+ years' technical experience; OR Master's in EE/CE/CS or related with 6+ years' technical experience; OR Bachelor's in EE/CE/CS or related with 8+ years' technical experience; OR equivalent practical experience. Fields include electrical/computer engineering, computer science, or related technical disciplines.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.