Principal / Sr. Staff Engineer, RTL Synthesis Methodology

Job Title

Principal / Sr. Staff Engineer, RTL Synthesis Methodology

Role Summary

Lead the technical direction and deployment of RTL-to-gate synthesis flows for Qualcomm SoCs across multiple technology nodes. Partner with RTL design, physical design, and EDA vendors to optimize power, performance, and area (PPA) and to achieve robust synthesis, low-power, STA, and LEC signoff.

Own synthesis methodology, low-power implementation, signoff convergence, tool roadmaps, flow automation, and mentoring of CAD engineers.

Experience Level

Senior — posting specifies 15+ years of experience in ASIC CAD flow development, Physical Design, or Synthesis Methodology. The posting also lists education-based minima (Bachelor's +8 years, Master's +7 years, PhD +6 years) as alternative qualification paths.

Responsibilities

Primary responsibilities include defining synthesis methodology, driving PPA improvements, and delivering signoff-quality flows.

• Define, develop, and deploy the global RTL synthesis reference flow (Synopsys Fusion Compiler, Cadence Genus) across technology nodes (5nm, 3nm, 2nm+).
• Lead RTL-to-GDS co-optimization initiatives with RTL and PD teams to improve PPA.
• Architect and maintain low-power (UPF/IEEE 1801) implementation methodology and static low-power checking.
• Own logic equivalence checking flows (Cadence Conformal, Synopsys Formality) and early STA signoff quality (PrimeTime, Fishtail).
• Engage with EDA vendors to drive tool roadmaps, manage evaluations, and specify critical enhancements.
• Oversee flow automation (Python, Tcl) to integrate synthesis with DFT insertion and netlist signoff.
• Mentor CAD engineers and provide technical guidance on complex debug and flow architecture.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 15+ years experience in ASIC CAD flow development, Physical Design, or Synthesis Methodology.
• Deep expertise with Synopsys Fusion Compiler / Design Compiler (DC-NXT) and Cadence Genus.
• Hands-on mastery of Logic Equivalence Checking tools (Cadence Conformal, Synopsys Formality) and ability to debug difficult non-equivalent points.
• Strong understanding of Static Timing Analysis and SDC constraints generation/validation (PrimeTime, Fishtail/GCA).
• Advanced scripting skills for flow development and data analysis (Python, Tcl).
• Proven ability to lead cross-functional projects and interact with EDA vendors.

Preferred / nice-to-have:

• Experience with UPF/CPF low-power flows, multi-voltage domains, power gating and retention techniques.
• Familiarity with Physical Synthesis approaches and correlation with P&R tools (Innovus/ICC2).
• Experience with RTL-integrated DFT flows (scan stitching, MBIST) and their timing/congestion impact.
• Experience with AI/ML-driven CAD tools for design space exploration (e.g., Fusion.ai, Cerebrus).

Education Requirements

Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering, or a related technical field. The posting specifies equivalency options: Bachelor's +8 years, Master's +7 years, PhD +6 years of relevant hardware engineering experience; equivalent practical experience is accepted where stated.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.