Principal Solutions Architect – Semiconductor Test

Job Title

Principal Solutions Architect – Semiconductor Test

Role Summary

Senior individual contributor responsible for defining and leading the technical strategy for semiconductor test across wafer probe, ATE, package/final test, and qualification. The role partners with development, process, product engineering, and manufacturing teams to modernize test infrastructure, improve yield, and embed data-driven intelligence across the test lifecycle.

Experience Level

Senior — typically requires 15+ years of hands-on semiconductor test engineering experience.

Responsibilities

Primary responsibilities include technical leadership of test architecture, cross-functional coordination, and mentoring.

• Define test development strategy for wafer-level (probe/ATE) and package/final/qualification tests for new and existing products.
• Lead architectural trade-offs on test coverage, test time, cost, and quality escapes across the full test flow.
• Establish guidelines for test program structure, modularity, and reuse across ATE platforms.
• Act as senior liaison for DFT architecture decisions (scan, BIST, JTAG, boundary scan, compression).
• Influence SoC and IP build reviews to ensure testability, observability, and debug capability.
• Drive adoption of AI/ML for yield learning, outlier detection, predictive binning, and test-time optimization.
• Define and maintain test roadmaps aligned with device technology and manufacturing scale targets.
• Mentor senior and principal test engineers and cultivate technical standards across the organization.
• Engage with ATE vendors, test IP providers, and standards bodies (SEMI, JEDEC, IEEE) on technology and standards.

Requirements

Must-have technical skills and experience; a short list of differentiators is provided under "nice-to-have."

• 15+ years of hands-on semiconductor test engineering experience in a fab, IDM, or OSAT environment.
• Deep expertise in at least three areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.
• Proven experience with ATE platforms such as Advantest V93000 or Teradyne UltraFLEX/ETS or equivalent systems.
• Strong practical experience with DFT architectures including scan compression, MBIST/LBIST, and JTAG.
• Proficiency in test-related scripting and automation (Python, Perl, C++, or platform-native languages).
• Proven ability to lead multi-site technical initiatives and influence cross-functional teams without direct authority.

Nice-to-have:

• Experience applying ML/AI to yield analysis, PAT/GDBN outlier screening, or adaptive test strategies.
• Familiarity with test data formats (STDF, ATDF) and analytics tools (JMP, Spotfire, or custom solutions).
• Experience with mixed-signal, RF, or high-speed I/O test and advanced packaging test challenges (2.5D/3D, chiplets, KGD).
• Prior engagement with SEMI standards committees or ATE vendor co-development programs.

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (MSEE, MSCE, MSCS) is typical, or equivalent practical experience. A Ph.D. or equivalent experience is listed as a plus.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.