Principal Silicon Design Subsystem Lead

Job Title

Principal Silicon Design Subsystem Lead

Role Summary

Lead design and verification for one or more custom SoC subsystems within Microsoft Silicon (AISoC), delivering IP and subsystem functionality that meets performance, quality, manufacturability, and scale requirements for cloud infrastructure.

Work with architects, design, and DV teams to define micro-architectural specifications, verification strategy, and drive delivery through silicon bring-up. This is an individual contributor technical leadership role.

Experience Level

Senior — typical minimum experience aligns with 8+ years for candidates with a Bachelor's degree; alternatives described in Education Requirements. Preferred: 12+ years of relevant experience and prior lead roles across cross-functional engineering teams.

Responsibilities

Primary responsibilities include subsystem technical leadership, verification strategy, and collaborations that enable production-quality silicon.

• Provide technical leadership for one or more SoC subsystems; own architecture-to-implementation correctness.
• Oversee development of custom subsystem IP and micro-architectural features.
• Create micro-architectural specifications with architects and translate them into verification plans.
• Define verification strategy, testplans, functional coverage, and drive coverage closure.
• Write and debug constrained-random stimulus, scoreboards, checkers, and assertions; develop UVM components and C++ tests.
• Debug RTL and run simulation/emulation workflows; collaborate on reuse across teams.
• Develop infrastructure scripts and makefiles to support verification flows; apply Agile practices including code review and sprint planning.
• Mentor and provide technical guidance to engineers across time zones and functions.

Requirements

Concise list of required skills, security, and other conditions. Education and degree/years details are in the Education Requirements section below.

• Must-have: Demonstrated technical leadership of IP or subsystem design and verification.
• Must-have: Extensive experience with IP/SS-level verification using Universal Verification Methodology (UVM) and C++ testbenches; constrained-random, scoreboards, assertions, and functional coverage.
• Must-have: Strong RTL debug experience and familiarity with simulation and/or emulation environments.
• Must-have: Proficiency in scripting (Python, Perl) and development of verification infrastructure (makefiles, automation).
• Must-have: Ability to meet Microsoft Cloud background check and export-control eligibility requirements.
• Nice-to-have: Experience with AI/ML SoCs, CPUs/VPUs/GPUs, DMA engines, or tensor units.
• Nice-to-have: Formal property verification experience and experience across multiple product cycles from definition to silicon.
• Nice-to-have: Experience with DFT implementation, static checks, and handoff to physical design.
• Willingness to travel up to ~25% as required.

Education Requirements

Options accepted per posting: Doctorate (PhD) in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years technical engineering experience; OR Master's degree in those fields with 6+ years experience; OR Bachelor's degree in those fields with 8+ years experience; OR equivalent practical experience. Related technical fields and equivalent experience are explicitly permitted.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.